2013
DOI: 10.1016/j.mejo.2013.04.008
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Single capacitor with current amplifier compensation for ultra-large capacitive load three-stage amplifier

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Cited by 9 publications
(9 citation statements)
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References 29 publications
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“…7 The simulation results for the slew rate of the proposed circuit Fig. 8 The simulation results for the bandwidth of the proposed circuit Table 1 summarizes the simulation results of the proposed buffer amplifier in HSPICE in comparison with other buffer amplifiers [6][7][8][9][10].…”
Section: Simulation Resultsmentioning
confidence: 99%
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“…7 The simulation results for the slew rate of the proposed circuit Fig. 8 The simulation results for the bandwidth of the proposed circuit Table 1 summarizes the simulation results of the proposed buffer amplifier in HSPICE in comparison with other buffer amplifiers [6][7][8][9][10].…”
Section: Simulation Resultsmentioning
confidence: 99%
“…There are many attempts to increase the performance of displays such as [6][7][8][9][10]. In [6], the designed circuit works well in terms of charging and discharging speed of large capacitors, but it has low bandwidth.…”
Section: Introductionmentioning
confidence: 99%
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“…Even so, most of the chip area is occupied by the compensation capacitors in large-capacitive-load amplifier [3]. So various frequency compensation strategies [1,3,4,5,6,7,8,9,10] are developed to reduce compensation capacitor and lower the power consumption.…”
Section: Introductionmentioning
confidence: 99%
“…The compensation technique presented in [8] can drive ultra-large capacitive load with a small compensation capacitor, yet the systematic offset voltage incurs due to the asymmetry of the first stage.…”
Section: Introductionmentioning
confidence: 99%