Single-Chip Implementation of Feature Measurement for LPC-Based Speech Recognition

Abstract

A single‐chip implementation of Linear Predictive Coding (LPC)‐based feature measurement for speech recognition, called the Feature Extracting Digital Signal Processor (FXDSP), has been developed by programming the AT&T DSP20™ programmable Digital Signal Processor (DSP) and has been verified by both numerical simulation and system use. For identical input, the recognition distance between floating point simulation and the DSP implementation was found to be negligibly small when compared with distances for word matches. The feature‐measurement technique is identical to that used in numerical simulations of LPC‐based isolated‐ and connected‐word recognition using combinations of dynamic time warping, vector quantization, and hidden Markov modeling. As a result, the FXDSP represents a single‐chip common building block for real‐time implementation of most speech recognition techniques under investigation at AT&T Bell Laboratories. The FXDSP performs eighth‐order LPC analysis on speech received from a standard CODEC. In every frame period (15 ms) it produces a feature vector consisting of the log energy, nine amplitude‐normalized autocorrelation coefficients, and nine LPC‐based test‐pattern coefficients. The feature‐measurement program requires 1023 locations of the 1024 available in on‐chip program ROM, 211 of 256 available RAM locations, and 75 percent of available real time.