Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise

Abstract

This paper introduces a 51.2Gops, 1.0GB/s-DMA single-chip multi-processor integrating quadruple cores and proposes a new power integrity analysis. Our multi-processor is designed to decode MP@HL streams without any dedicated circuits. To achieve such high performance, data throughput as well as processing capability is important, requiring a large number of high speed I/Os. However, this makes for a high level of power supply noise. We then applied an interface timing margin analysis tool that took power supply noise into account, and succeeded in putting reasonable restrictions on LSI design, as well as that for the printed circuit board. As a result, we succeeded in operating the processor at 533MHz with the 2ch 64bit main memory IF at 266MHz and 64bit system bus at 178MHz. Driver input port Receiver input port DIE PKG PCB Receiver LSI PKG PCB Driver LSI DIE Receiver LSIApply the power supply voltage waveforms of DIE, PKG, and PCB