2018 7th Mediterranean Conference on Embedded Computing (MECO) 2018
DOI: 10.1109/meco.2018.8406022
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Single clock square root algorithm based on binomial series and its FPGA implementation

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Cited by 4 publications
(3 citation statements)
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“…4, which demonstrates that positive and negative peaks are equal. Despite low absolute (22) and relative ( 25) errors of approximation with hyperbolas coinciding with target parabola at borders of interval of approximation, these errors can be decreased more, if zero errors at the end of this interval are not needed (the error function may not be continuously differentiable). In this case, we can change the criteria for definition of hyperbola coefficients.…”
Section: Proposed Methodsmentioning
confidence: 99%
“…4, which demonstrates that positive and negative peaks are equal. Despite low absolute (22) and relative ( 25) errors of approximation with hyperbolas coinciding with target parabola at borders of interval of approximation, these errors can be decreased more, if zero errors at the end of this interval are not needed (the error function may not be continuously differentiable). In this case, we can change the criteria for definition of hyperbola coefficients.…”
Section: Proposed Methodsmentioning
confidence: 99%
“…In addition, Johnson [15], provided an iterative procedure for computing square root. Knill [16], on the other hand developed a modified Babylonian method for calculating square root and Dubeau [17], used a double iteration method to calculate general roots. Bagala et.…”
Section: Introductionmentioning
confidence: 99%
“…Square rooting algorithm is often employed in field programmable gate array applications of image processing [20], spectrum analyser [26] and many others. Bagala et al [17,27] proposed a single clock square root algorithm applicable in field programmable gate array.…”
Section: Introductionmentioning
confidence: 99%