Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology

Abstract

Although near-threshold (V th ) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, for static random access memory (SRAM) cells. This brief proposes a near-V th 9T SRAM cell implemented in a 22-nm FinFET technology. The read buffer of the proposed cell ensures read stability by decoupling the stored node from the read bit-line and improves read performance using a one-transistor read path. Energy and standby power are reduced by eliminating the sub-V th leakage current in the read buffer. For accurate sensing yield estimation, a new yield-estimation method is also proposed, which considers the dynamic trip voltage. The proposed SRAM cell can achieve a minimum operating voltage of 0.3 V.Index Terms-Fin-shaped field-effect transistor (FinFET), low-power design, near-threshold static random access memory (SRAM), single-ended sensing. 1063-8210

Transmission gate‐based 9T SRAM cell for variation resilient low power and reliable internet of things applications

“…The H POWER of post-layout simulation is found to be lower than pre-layout (schematic) simulation because of the increased parasitic resistances. Table 4 Comparison of V DD,min for all the compared cells Design metrics S6T 7T [23] FD8T [27] SEDF9T [6] LP9T [30] RD9T [41] SB9T [42] This work (TG9T) min for WSNM, mV 443 194 443 540 566 443 635 195 RSNM, mV 462 351 462 200 340 200 200 287 HSNM, mV 200 209 200 200 224 200 200 209 effective V DD,min , mV 462 351 462 540 566 443 635 287…”

“…In this study, a TG9T SRAM cell is proposed for IoT application. TG9T has mainly been compared with other similar-sized SRAM Table 6 Comparison among different SRAM cells Design metrics S6T 7T [23] FD8T [27] SEDF9T [6] LP9T [30] RD9T [41] SB9T [42] This work (TG9T) V 2 EQM = RSNM × HSNM × WSNM T RA × T WA × H POWER × P READ × P WRITE × (σ/ μ)T RA × (σ/ μ)T WA × V DD, min × Area .…”

“…A comparison of the relevant design metrics for SRAM cells has been given in Table 6. In addition to 7T, FD8T and SEDF9T, four other cells namely standard 6T (S6T), LP9T [30], RD9T [41] and SB9T [42] with appropriate sizes are compared with the proposed TG9T cell. From the table, it is evident that TG9T shows great advantages in terms of write ability with the highest WSNM among the compared cells except for 7T cell.…”

PAOD: a predictive approach for optimization of design in FinFET/SRAM

“…Chen et al [13] have introduced a technique for facilitating an effective writing operation for reducing the supply voltage. Yang et al [14] addressed the problem associated with near-threshold based operation improving the reading performance. Karl et al [15] has developed a prototype design of SRAM emphasizing on collapsing voltage for minimizing energy consumption during write operation.…”

Design of Ultra-Low Voltage/Power Circuits and Systems

“…Over the last years, the Internet of Things (IoT), wireless sensor networks and the emergence of other energy-constrained applications have pushed the demand for low-cost systems-on-chip solutions, entailing tight area and small power/voltage budgets [1,2]. In response to such requests, considerable effort has been spent in defining novel ultra-low voltage/power analog (e.g., [3][4][5][6]), mixed-signal (e.g., [7][8][9]), digital circuits (e.g., [10][11][12]), as well as energy-efficient and high-density memory solutions [13][14][15][16].…”