Single-ended input four-quadrant multiplier for analog neural networks

Aksin, Devrim Yılmaz; Basyurt, Pinar Basak; Uyanik, Hayri Ugur

doi:10.1109/ecctd.2009.5274983

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Cited by 4 publications

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“…The increasing demand for low voltage/low-power integrated circuits has encouraged the development of CMOS currentmode architectures. As in their voltage-mode counterparts, the operation principle of most available current-mode structures lays on drain current either deep in strong inversion [5][6][7] or in weak inversion region [8][9]. In both cases linearity becomes poorer as the amplitude of input signals increases.…”

Section: Introductionmentioning

confidence: 99%

Analog Multiplier Based on Squarer Cells

Zarei

Maali

2019

IJSRSET

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In this paper, a current-mode analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18µm technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. Simulations are performed by HSPICE for the circuit to prove its great merits of; low power consumption (100µW), low supply voltage (1.6V), body effect immunity, wide input range (±100nA), bandwidth of 1 MHz, and THD of 4%.

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