Single event effect testing of the Intel 80386 family and the 80486 microprocessor

Moran, A.K.; LaBel, Kenneth A.; Gates, Michele; Seidleck, C.M.; McGraw, Richard J.; Broida, Michael S.; Firer, J.; Sprehn, S.

doi:10.1109/23.510728

Cited by 9 publications

(4 citation statements)

References 1 publication

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“…Accelerator test results, however, showed that the soft error rate of an application seemed to be tightly related with cache usage in such microprocessors [1] [2]. For safety critical systems, cache memory content are usually froze, e.g.…”

Section: Backgroundandprevious Workmentioning

confidence: 97%

“…the A320 AIRBUS flight control computer [3]. In [1], Moran has demonstrated an order of magnitude higher susceptibility of 80486 processors when the cache is on as compared to when it is off. In [2], Rufenacht showed that the SEU rate for an identical application increase almost an order of magnitude, when cache is enabled, in ISS and POLAR orbits, almost two orders of magnitude in ROEMER orbit, and even much higher than three orders of magnitude in a GEO orbit.…”

Section: Backgroundandprevious Workmentioning

confidence: 97%

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A New Method for Measuring Single Event Effect Susceptibility of L1 Cache Unit

Zhou

Yang

Wang

2008

2008 Second International Conference on Secure System Integration and Reliability Improvement

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Cache SEE susceptibility measurements are required for predicting processor's soft error rate in space missions. Previous dynamic or static real beam test based approaches are only tenable for processors which have optional cache operating modes such as disable(bypass)/enable, frozen, etc. As L1 cache are indispensable to the processor's total performance, some newly introduced processors no longer have such cache management schemes, thus make the existed methods inapplicable. We propose a novel way to determine cache SEE susceptibility for any kind of processors, whether cache bypass mode supported or not, by combining heavy ion dynamic testing with software implemented fault injection approaches. Background&Previous WorkCache are usually introduced to enhance overall performance of a microprocessor since the improvement of memory bandwidth lags largely behind that of CPU clock frequency. Accelerator test results, however, showed that the soft error rate of an application seemed to be tightly related with cache usage in such microprocessors[1] [2]. For safety critical systems, cache memory content are usually froze, e.g. the A320 AIRBUS flight control computer [3]. In[1], Moran has demonstrated an order of magnitude higher susceptibility of 80486 processors when the cache is on as compared to when it is off. In [2], Rufenacht showed that the SEU rate for an identical application increase almost an order of magnitude, when cache is enabled, in ISS and POLAR orbits, almost two orders of magnitude in ROEMER orbit, and even much higher than three orders of magnitude in a GEO orbit. There exists some processor simulator based analytical approaches to analyze cache vulnerability for both L1 and L2 cache memories which do not require a real beam of energetic particles[4] [5]. However, such simulation based methods cannot provide quantitative results. Previous methods to measure cache SEE susceptibility can be classified into static test approaches and dynamic ones. In[6]and[7], Irom et al. proposed a static method by initializing the L1 cache memories with a known pattern before irradiation, and then turned the processor into cache frozen mode, compare cache memory contents after irradiation with its golden copy will provide number of upsets occurred during accelerator test. Such method takes advantage of PowerPC processors' cache frozen ability which can keep cache contents steady but the readback and verification procedure of cache contents were not clearly addressed in these papers. Instead of that, the test Moran and Rufenacht have done uses dynamic methods. Cache memories could be modified automatically by cache controller with the application programm running as it is. Therefore, they need a cache free version of SEE behavior to analyze the role of cache out of the total SEE induced errors observed during irradiation, since the application's soft error rate would also be affected by other sensitive nodes such as L2 SRAM, registers, etc. They achieved this by doing the same test procedure using the same version of...

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Section: Backgroundandprevious Workmentioning

confidence: 97%

Section: Backgroundandprevious Workmentioning

confidence: 97%

A New Method for Measuring Single Event Effect Susceptibility of L1 Cache Unit

Zhou

Yang

Wang

2008

2008 Second International Conference on Secure System Integration and Reliability Improvement

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“…This error is serious because it cannot essentially be corrected by usual Error Correction Code (ECC). Though some of them are supposed to be due to "known" mechanism like latch-up or "microlatch", their detailed phenomena and mechanisms have not been identified yet [3][4][5].…”

Section: Introductionmentioning

confidence: 97%

Novel Mechanism of Neutron-Induced Multi-Cell Error in CMOS Devices Tracked Down from 3D Device Simulation

Yamaguchi

Ibe

Yamamoto

et al. 2006

2006 International Conference on Simulation of Semiconductor Processes and Devices

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In recent CMOS devices, multi-cell error induced by cosmic neutron, in which memory state change extends over multiple memory cells, is becoming serious. However, its mechanism has not been clarified yet because conventional analysis by device simulation has not included multiple memory cells domain. Our novel method is to create the device model including multiple memory cells and perform 3D simulation. Analyzing current transients and current distribution, we identified multi-cell error as a chain reaction as follows: (1) parasitic bipolar in "target" CMOSFET is turned on by secondary ions produced by ion strike, (2) this parasitic bipolar action causes well voltage shift, (3) lastly parasitic bipolar in adjacent CMOSFETs are turned on and thus error propagates.

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“…More information is needed on how complex ASICs respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltages than recent devices [1]- [6].…”

Section: Introductionmentioning

confidence: 99%

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

Irom

Farmanesh

Kouba

2006

IEEE Trans. Nucl. Sci.

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Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.Index Terms-Cyclotron, heavy ion, microprocessors, silicon on insulator.

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Single event effect testing of the Intel 80386 family and the 80486 microprocessor

Abstract: We present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored.

Cited by 9 publications

References 1 publication

A New Method for Measuring Single Event Effect Susceptibility of L1 Cache Unit

A New Method for Measuring Single Event Effect Susceptibility of L1 Cache Unit

Novel Mechanism of Neutron-Induced Multi-Cell Error in CMOS Devices Tracked Down from 3D Device Simulation

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

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