Single event effects in static and dynamic registers in a 0.25 /spl mu/m CMOS technology

Abstract

We have studied Single Event Effects in static and dynamic registers designed in a quarter micron CMOS process. In our design, we systematically used guardrings and enclosed (edgeless) transistor geometry to improve the total dose tolerance. This design technique improved both the SEL and SEU sensitivity of the circuits. Using SPICE simulations, the measured smooth transition of the cross-section curve between LET threshold and saturation has been traced to the presence of four different upset modes, each corresponding to a different critical charge and sensitive area. A new architecture to protect the content of storage cells has been developed, and a threshold LET around 89 MeVcm'mg.' has been measured for this cell at a power supply voltage of 2 V.

Single event effects in the pixel readout chip for BTeV

“…A decrease of the energy threshold for single bit upset has been reported in reference [4] for a static register in clocked mode with respect to unclocked mode. Our data, taken with a clock frequency of 380 kHz, do not show a statistically significant difference from the data taken in the unclocked mode.…”

“…The sensitive volumes are smaller for small feature size technology than for larger feature size technology. There are circuit hardening techniques to mitigate single event upset [4], but usually these require an increase of the circuit area, complexity, and power consumptions -all factors already constrained in a readout chip for pixel sensors.…”

Radiation hazard of relativistic interstellar flight

“…The measured SEE in CMOS (Faccio, 1999) is approximately 2.6 10 -7 cm 2 /bit for particles' LETs (Linear Energy Transfer) above 20 MeV cm 2 /mg with dramatic decrease below 14 MeV cm 2 /mg. The laboratory tests of irradiation of various electronic components by protons and heavy ions are described by LaBel at al.…”

“…The deposition of charge can "upset" the memory circuits. The so-called Single Event Effects (SEEs) and Single Event Upsets (SEU) in computer memory are being intensively studied in high-altitude avionics (Normand, 1996), on satellites, and in multiple laboratory tests (Faccio, 1999;1997). Upset rate of a particular part of electronic equipment from cosmic radiation in the vicinity of Earth can vary from ten per day for commercial one-megabit RAMs, to 1 every 2800 years for radiation-hardened onemegabit RAMs (radiation-hardened component is a device that has been specially designed and built to resist ionizing radiation).…”

Radiation qualification of the front-end electronics for the readout of the ATLAS liquid argon calorimeters

“…The layouts made systematic use of an enclosed transistor topology and guard rings to prevent any radiation-induced leakage current under the thick isolation oxide. The data-latch and SRAM standard cells have been designed to be single-event upset (SEU) resistant [23]. In the circuit designs, considerable mitigation techniques were employed to reduce the sensitivity to SEE.…”