Single event upset at ground level

Normand, E.

doi:10.1109/23.556861

Cited by 515 publications

(183 citation statements)

References 25 publications

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“…We will here address on SEU effects. SEU originates many soft errors in ICs operating in space or high atmosphere as previously reported in [2][3][4], but also at ground level in terrestrial computer electronics as evidenced by IDM [1] or Normand [5]. The consequences of this effect are enhanced by scaling and the emergence of blocks embedded in System-on-Chip (SoC), difficult to test.…”

Section: Introductionmentioning

confidence: 96%

Integration of Robustness in the Design of a Cell

Dutertre

Roche

Cathébras

2002

IFIP Advances in Information and Communication Technology

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Abstract:When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits undergo soft errors. Among these events the most worrying is an electrical upset, so called Single Event Upset (SEU) evidenced in latches. We present here the circuit architecture of a new SEU hardened latch. The hardening is based on an integrated redundancy of the information and a high impedance state switching. The design prevents perturbation to propagate inside the latch and saves an uncorrupted information source for recovery mechanisms. Post layout circuit simulations are used to verify the hardness assurance of this design; we also compare it to usual techniques and report significant improvements for its use in SoC.

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Section: Introductionmentioning

confidence: 96%

Integration of Robustness in the Design of a Cell

Dutertre

Roche

Cathébras

2002

IFIP Advances in Information and Communication Technology

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“…These latter effects due to ionizing particles of cosmic origin, alpha and neutrons, were deeply studied in space [7], but were also observed at ground level [8] and at flight altitude [9]. These faults usually cause the change of a stored bit (soft error -SE) in a memory cell and are modeled as bit-flip.…”

Section: Project Goalmentioning

confidence: 99%

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Bolchini

Miele

Sandionigi

et al. 2012

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for mission- and safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC)

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“…3 At ground level, neutrons are the most frequent causes of upsets. 4 When a single heavy ion strikes the silicon, it loses its energy through the production of free electron-hole pairs, resulting in a dense ionized track in the local region. Protons and neutrons can cause a nuclear reaction when passing through the material.…”

Section: Radiation Effects On Sram-based Fpgasmentioning

confidence: 99%