Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Abstract

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-oninsulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled.

Protecting Big Blue from Rogue Subatomic Particles

“…Each injected current pulse wave shape follows a sharp linear rise with an exponential decay, as introduced in [15], [16]. The results are verified against simulations conducted using the drift-diffusion device simulator Fielday [17], [18], and against hardware measurements [8]. Figure 7, from [1], compares simulated and measured Qcrit values for the 65nm SOI slave latch measurements shown in Figure 3 and Table I.…”

“…The 3 MV Tandem Van de Graaff accelerator at the IBM T. J. Watson Research Center is used to measure Qcrit in SOI circuits [8] and the sensitivity of circuits to a columnated, monoenergetic radiation source [9], [10]. The lab has seven beam lines, one of which is dedicated to single event upset exposures.…”

“…At the critical angle where SEUs just begin, the deposited charge is equal to Qcrit. Figure 3 presents the measured fail rate of a 65nm SOI master-slave flip flop as a function of chip angle with respect to beam, from [8]. Data is shown for two different data transitions for both the master (LI) and slave (L2) stages, with the critical angle indicated.…”

“…FOR 65NM SOI MASTER-SLAVE FLIP FLOP OBTAINED AT VDD = 1.OV FROM 5.3 MEV a-PARTICLE MEASUREMENTS IN TANDEM ACCELERATOR.TABLE REPRODUCED FROM[8].…”

Design, Analysis and Test of Logic Circuits Under Uncertainty

“…They are emitted by radioactive elements, such as the uranium or lead isotopes in chip-packaging materials. When packaging materials were improved in the 1980s, the problem was eliminated to a large extent; however, as device technologies scale down towards 32nm, the particle energy required to upset the state of registers and memory circuits becomes smaller [41]. Figure 1.2 shows that even at 1.25 MeV, incident particles can alter the state of latches, depending on the angle of incidence.…”