Single phase clocked quasi static adiabatic tree adder

Sasipriya, P.; Bhaaskaran, V. S. Kanchana

doi:10.1109/icdcsyst.2012.6188723

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Complementary Energy Path Adiabatic Logic1

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“…Similarly the weak low signal is also eliminated by the complementary clock. [22]- [24] Let us assume the other case in which Vout is high with the P-network on and the N-network is off. The Vout remains high unless and until there is a change in the input.…”

Section: Complementary Energy Path Adiabatic Logicmentioning

confidence: 99%

Design of Low Power 4-bit ALU Using Adiabatic Logic

Turaga¹,

Vanama²,

Gunnuthula³

et al. 2014

IOSRJVSP

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This paper presents the implementation of a 4-bit Arithmetic Logic Unit (ALU) using Complementary Energy Path Adiabatic Logic (CEPAL). This static adiabatic logic has proved its advantage through the minimization of the 1/2CVdd2 energy dissipation occurring every cycle. Firstly, the performance characteristics of CEPAL 4-to-1 multiplexer and full adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. Finally, A 4-bit Arithmetic Logic Unit (ALU) is implemented with both the technologies and comparisons have been made. The analysis is carried out using the industry standard EDA design environment using 250 nm technology libraries from Tanner. The results prove that the CEPAL 4-bit ALU is 55% more power efficient than the CMOS 4-bit ALU at 100MHz and at 2.5V operating voltage.

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Section: Complementary Energy Path Adiabatic Logicmentioning

confidence: 99%