“…In [127], authors have used fault current limiter to reduce the UPQC rating particularly by limiting the excessive current during the event of a fault. Finally, it is found that throughout the development phases of UPQC, researchers have given equal importance to evaluate the control algorithm and overall UPQC system performance by experimental investigation [11], [14], [22], [23], [26], [33], [40], [42], [51], [52], [56], [57], [60], [63], [75], [80], [81], [89], [94], [97], [107], [109], [114], [116]- [118], [120], [129], [143]- [145], [147], [150], [155]- [157], [159], [161], [163], [164], [167], [168]. A 250-kVA UPQC system is developed at the Centre for the Development of Advanced Computing (C-DAC), Thiruvananthapuram, India [75].…”