Sinusoidal Clocked Sense-Amplifier-Based Energy Recovery Flip-Flops

Abstract

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-ampli¯er based°ip-°op (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed°ip-°op operating with energy recovery single phase sinusoidal clock shows better performance. The proposed°ip-°op also reduces the leakage current and glitch.