1995
DOI: 10.1149/1.2043901
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SiO2 / Si Interface Structures and Reliability Characteristics

Abstract: This paper shows that a structural transition layer of SiO2 exists at an SiO~/Si interface prepared by thermal oxidation of St. Using a newly developed grazing-incidence x-ray diffraction of synchrotron radiation, the transition layer density (2.4 g/cm 3) is found to be lower than the immediate bulk SiO2 density (2.6 g/cm3), and its thickness is approximately 7 nm. Electrical properties of the SiO2 films are examined by using Fowler-Nordheim tunneling electrons which are injected from the polycrystalline silic… Show more

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Cited by 100 publications
(33 citation statements)
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“…5 (modified from [9]), which shows two possible inelastic TAT modes. The model assumes available defects for as-grown and stressed SiO 2 , which is quite well established and generally accepted, particularly for near bottom interface [10]. Process (a) represents FN tunneling at the top interface and subsequent TAT or direct tunneling, which would have Φ dependence.…”
Section: Resultsmentioning
confidence: 99%
“…5 (modified from [9]), which shows two possible inelastic TAT modes. The model assumes available defects for as-grown and stressed SiO 2 , which is quite well established and generally accepted, particularly for near bottom interface [10]. Process (a) represents FN tunneling at the top interface and subsequent TAT or direct tunneling, which would have Φ dependence.…”
Section: Resultsmentioning
confidence: 99%
“…This Qw degradation, which is due to boron incorporation in the dielectric film, is a serious problem for a surface channel PMOS transistor with a thinner oxide film. The boron diffusion and incorporation enhance creation of the strained and broken Si-0 bonds in a structural transition layer (STL) near the dielectric/substrate interface [7]. In a thinner film, the STL occupies a larger part of the film (Fig.…”
Section: Resultsmentioning
confidence: 99%
“…While for nMOS devices, apparently the superior oxide robustness under substrate injection polarity (i.e., highly positive potential) protects the devices from charging damage at the wafer edge. The strong polarity dependence of was believed to be due to the weakness of structure transition layer (STL) located in the SiO /Si interface [15], [16]. The injected energetic electrons may release energy at the STL interface and cause bond breaking, a precursor of dielectric breakdown, under gate injection.…”
Section: A Plasma Charging Damage In Nmos and Pmos Devices 1) Indicamentioning
confidence: 99%
“…The formation of strong Si-N bonds in place of strained Si-O bonds and weak Si-H bonds enhances the interface hardness, resulting in improved gate oxide integrity [3]. Since it has been speculated that trap creation mechanism responsible for SILC is hydrogen-related, the incorporation of nitrogen by N O-nitridation is expected to terminate Si dangling bonds at the SiO /Si interface as well as to reduce the stress/strain in the structure transition layer (STL) [15], [24]. As a result, gate leakage current after plasma charging can be reduced.…”
Section: ) Suppression Of Gate Leakage Current Due To Charging Damagmentioning
confidence: 99%