SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC

Abstract

Today's embedded systems require resource-aware acceleration engines, which support advanced cryptographic algorithms such as elliptic-curve cryptography (ECC). The authors present an application-specific co-processor for digital signature verification according to the Elliptic Curve Digital Signature Algorithm (ECDSA) based on the NIST B-233 standard. A novel OpenRISC-ISA (instruction-set architecture) core featuring a high IPC rate and balanced pipeline stages has been developed to act as the main controlling unit of the accelerator. The redesigned OpenRISC core processes 67 % more instructions per second than the reference architecture and ties with a micro-controllable ECC datapath through a highly optimized interface. An ECDSA signature is verified in 11 ms, which is equal to a speedup of 15x and 3.3x with respect to a portable C implementation on the OpenRISC and an assembler-optimized implementation on an ARM7, respectively. Moreover, thanks to a tightly coupled data memory, the proposed co-processor does not block the OpenRISC during its ECC-specific operations, thereby enabling it to also support concurrent execution of other workloads and/or softwarebased cryptographic extension functions.

Empirical derivation of upper and lower bounds of NBTI aging for embedded cores

“…We do not mark all of them since there are too many of them (For instance, we do not mark first year aging frequency points because the critical path always changes during the first year). For instance of OR10N core under high frequency with all signals have 0.7 static probability, the fresh critical path is from signal id stage i/alu operator ex o reg [2] and ends with signal id stage i/alu operand b ex o reg[31]; then the critical path changes to one from signal id stage i/mult signed mode dot ex o reg[0] and ends with signal id stage i/mult operand b dot ex o reg [25] at first year; it changes again to the one from signal id stage i/mult signed mode dot ex o reg[0] and ends with signal id stage i/mult operand b dot ex o reg [28] after two years. Aging effects of all three cores are now sizable, the difference 10-year aging between the worst-case (all signals at 0.0 probability) and the case with all signals at 0.99 probability is very obvious.…”

Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores

“…A RISC architecture is well-suited to be integrated in a tightly-coupled multi-core cluster because of its low area footprint and the low pipeline depth allowing to interact with other processors in a single cycle. In a previous work we developed OR10N, a complete redesign of the micro-architecture in order to balance pipeline stages, and increase IPC [4]. The redesigned core is divided into four pipeline stages, instruction fetch (IF), instruction decode (ID), execute (EX), and write back (WB) and achieves near-optimal IPC values of 1.…”

“…All operations can be completed in a single cycle except for multiplications which are pipelined once, and can lead to stalls if the result is used in the subsequent cycle. While the core was being attached to an instruction and data memory [4], it has now been integrated in a PULP-cluster by connecting it to an I$ and a low-latency interconnect. Implemented in the cluster, the OR10N core utilizes 35.5 kGE.…”

“…The OpenRISC ISA supports full 64 bit result multiplications and MAC operations, which cannot be implemented within a single cycle without impacting the maximum frequency. In a previous implementation [4], the multiplication was realized with a two cycle multiplier and MAC operations were based on a special purpose accumulator which is accessible through special instructions. Given the fact that the full 64 bit result is often not required, and that the compiler is not always able to group instructions in a way such that no stalls occur, we have decided to simplify the multiplication by only generating the 32-bit results.…”

“…In our work we have chosen the OpenRISC architecture which is a) open source and suitable to be optimized to work in a multi-core environment, and b) shows a low area footprint with only 35.5 kGE which allows the core to achieve an energy efficiency of 25.8 µW/MHz in 65 nm technology, which is competitive with an ARM Cortex M4 with an energy efficiency of 32.8 µW/MHz at similar area costs in a 90 nm technology [3]. While the computational efficiency of the OpenRISC architecture has been improved in terms of instructions per cycle (IPC) [4], it is missing important DSPlike features which allow a Cortex M4 to execute a program in less cycles due to its enriched instruction set. Enhancing an instruction set with very specific instructions is the key to increase performance in application-specific computing [5].…”