SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling

Deschinkel, Karine; Touati, Sid; Briais, Sébastien

doi:10.1007/s10878-010-9332-8

Cited by 2 publications

(8 citation statements)

References 22 publications

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“…Now the problem that must be solved by SIRA is to compute a valid reuse graph with minimal er ∈E reuse,t μ t (e r ), without increasing the initiation interval II if possible. Also, instead of minimising the register requirement, SIRA may simply look for a solution such that er ∈E reuse,t μ t (e r ) ≤ R t , where R t is the number of available registers of type t. We may propose many exact method models (the problem has been proved NP-complete in [22]) or heuristics based on the SIRA framework [8,21].…”

Section: Periodic Register Constraintsmentioning

confidence: 99%

“…There are many heuristics and methods that may be used. SIRALINA [8,21] is our most powerful method, we have already demonstrated that it a really efficient heuristic for SIRA: it considers an initial DDG with multiple register types, and produces an associated DDG to bound or to minimise the register requirement before SWP. SIRALINA is a two steps heuristic, with an algorithmic complexity equal to O( V 3 log V ), where V is a notation for the cardinality of a set.…”

Section: Application To the Sira Framworkmentioning

confidence: 99%

“…SIRALINA is a two steps heuristic, with an algorithmic complexity equal to O( V 3 log V ), where V is a notation for the cardinality of a set. It has been shown that SIRALINA, applied on a large set of benchmarks [8,21], is fast and efficient in practice. So it has been connected to an industry quality compiler for embedded systems targeting VLIW ST231 processors.…”

Section: Application To the Sira Framworkmentioning

confidence: 99%

“…Computing a valid reuse graph for a fixed period II that minimises er ∈E reuse,t μ t (e r ) is NP-complete [22]. SIRALINA heuristic [8,21] computes an approximate solution to this problem for all register types conjointly. In order to balance between the importance of each involved register type, we assume to have a weight α t ∈ R attributed to each type t ∈ T .…”

Section: Recall On Siralina Heuristicmentioning

confidence: 99%

“…The separation between register and resource constraints is an old debate in the community, recent arguments are presented in [21]. Furthermore, a recent efficient heuristic on this topic has been published in [8]. In this recent article the problem of non-positive circuits were not solved.…”

Section: Introductionmentioning

confidence: 99%

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How to eliminate non-positive circuits in periodic scheduling: a proactive strategy based on shortest path equations

Touati¹,

Briais

Deschinkel

2013

RAIRO-Oper. Res.

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Usual periodic scheduling problems deal with precedence constraints having non-negative latencies. This seems a natural way for modelling scheduling problems, since task delays are generally nonnegative quantities. However, in some cases, we need to consider edges latencies that do not only model task latencies, but model other precedence constraints. For instance in register optimisation problems devoted to optimising compilation, a generic machine or processor model can allow considering access delays into/from registers. Edge latencies may be then non-positive leading to a difficult scheduling problem in presence of resources constraints. This research result is related to the problem of periodic scheduling with storage requirement optimisation; its aims is to solve the practical problem of register optimisation in optimising compilation. We show that pre-conditioning a data dependence graph (DDG) to satisfy register constraints before periodic scheduling under resources constraints may create circuits with non-positive distances, resulted from the acceptance of non-positive edge latencies. As a compiler construction strategy, it is forbidden to allow the creation of circuits with non-positive distances during the compilation flow, because such DDG circuits do not guarantee the existence of a valid instruction schedule under resource constraints. We study two solutions to avoid the creation of these problematic circuits. A first solution is reactive, it tolerates the creation of non-positive circuit in a first step, and if detected in a further check step, makes a backtrack to eliminate them. A second solution is proactive, it prevents the creation of non-positive circuits in the DDG during the register optimisation process. It is based on shortest path equations which define a necessary and sufficient condition to free any DDG from these problematic circuits. Then we deduce a linear program accordingly. We have implemented our solutions and we present successful experimental results.Register optimisation is a broad research topic in optimising compilation since long time. We must distinguish three possible phase orderings between register optimisation and instruction scheduling:1. Register constraints are handled after instruction scheduling. This topic is called register allocation, and is well studied mathematically in [1-3] for acyclic

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Section: Periodic Register Constraintsmentioning

confidence: 99%

Section: Application To the Sira Framworkmentioning

confidence: 99%

Section: Application To the Sira Framworkmentioning

confidence: 99%