Size Dependence of Surface-Roughness-Limited Mobility in Silicon-Nanowire FETs

Transport and noise properties of graphene-based transistors revealed through atomistic modelling

“…Deviations occur for wider GNRs and for smaller H. As shown in Figure 1b, in narrower GNRs the higher the electron density, the larger the effective mobility, because of stronger screening. As already observed in Silicon Nanowire FETs [8], ȝ LER decreases for high n 2D and wider GNRs, due to modemixing. Figure 1c shows ȝ LER as a function of H, where ȝ LER ∝1/H for wide GNRs, as also observed in graphene in the presence of defects [9].…”

Epitaxial Growth of Ordered In-Plane Si and Ge Nanowires on Si (001)

“…Moreover, by selectively etching Si, stacked SiGe NWs were obtained to improve the channel mobility [7]. However, the top-down fabrication introduces atomic surface roughness and damages, which deteriorate the carrier mobility of the NWs [8].…”

Quantum transport models based on NEGF and empirical pseudopotentials for accurate modeling of nanoscale electron devices

“…As a matter of fact modern CMOS FETs resemble quantum constrictions connecting the source/drain carrier reservoirs 2 , however a full-band quantum transport formalism is theoretically complex and computationally very demanding, so that in the electron devices community it is still popular to use simplified Hamiltonians based either on the effective mass approximation (EMA) [8][9][10] , or on the k•p approach [11][12][13] . Both the EMA and k•p methods are known to provide a description of low dimensional systems that is limited to the vicinity of a) Electronic mail: marco.pala@c2n.upsaclay.fr b) Electronic mail: david.esseni@uniud.it a given symmetry point in the reduced zone of the underlying semiconductor, as well as known to have accuracy limitations in strongly confined systems.…”