SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems

Lin, Jai-Ming; Hung, Zhi-Xiong

doi:10.1109/tvlsi.2011.2104983

Cited by 32 publications

(23 citation statements)

References 38 publications

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“…Eventhough B*tree [9] and sequence pair [10] representation performs better in MSV floorplanning, SKB tree take less time to floorplan with wire length and power as its constraints. Every parent node in the SKB tree is has ordered nodes, arranged one after another without left child.…”

Section: Multiple Supply Voltage Floor Planningmentioning

confidence: 99%

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

Srinath¹,

Priya²,

Kasliwal³

2018

IJET

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In Contemporary Integrated Circuits (IC), the Voltage drop in the power rails and Electron migration risk (EM) due to high current densities are the most important factors degrading the reliability of the chip. The effect of these factors leads to an imbalance in the flow of charge carriers and voids in interconnects. This paper resolves the above issues, through analyzing and predetermining it in a Multiple Supply Voltage (MSV) design during the floorplanning stage. Simulations were carried out in Cadence digital Encounter system with 180nm technology for the circuit net list of 8 point FFT (Fast Fourier Transform) and FIR filter. Results show that floorplanning scheme is powerful in reducing 100% of voltage drop and 50% of EM risk in the chip as compared to previous works.

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Section: Multiple Supply Voltage Floor Planningmentioning

confidence: 99%

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

Srinath¹,

Priya²,

Kasliwal³

2018

IJET

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“…Different methods have been proposed for rectangular voltage islands (RVI) aware floorplanning [4] [2] [11]. Chen et al [2] proposed a practical method to floorplan with voltage island generation.…”

Section: Introductionmentioning

confidence: 99%

Irregularly shaped voltage islands generation with hazard and heal strategy

Meng¹,

Chen²,

Huang³

2015

Sixteenth International Symposium on Quality Electronic Design

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1Irregular Shaped Voltage Islands (ISVI) can achieve much better power savings in multiple supply voltage (MSV) technology. This paper proposes a simulated annealing (SA) based floorplanning method with ISVI generation using a Hazard and Heal strategy. In each perturbation of SA, a randomly chosen block is removed from floorplan and then inserted back to a proper position, to join certain voltage island. The solution space for every iteration is O(n 2 k vi ), where n is block number and k vi is voltage island number. Every position with voltage island assignment is evaluated by a linear combination of chip area, wire length, power and voltage island cost. To avoid timing-consuming evaluation of O(n 2 k vi ) possibilities, we propose a fast Hazard method to construct ISVI by skipping lots of distant voltage island candidates while occasionally accepting seldom-emerged illegal (non-contiguous) candidates. To resolve the seldom-emerged non-contiguous voltage islands, a detailed Heal method is applied in each temperature. Experimental results show the proposed method is effective and efficient compared with the latest works.

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“…To evaluate the P/G network resource of VI generation in multi-voltage SoC, many researchers [5], [6] adopt the model defined by Lee et al [7], which is k i=1 u i , where k is the number of VIs and u i is the half perimeter wirelength of the bounding box of island i. The model is a rough estimation which lacks P/G network details such as power pad locations and P/G network topology.…”

Section: Introductionmentioning

confidence: 99%

“…Do voltage partitioning to generate the desired K VIs[5];4 Identify the VIs in the floorplan and do power pad assignment for each power domain;5 Analysis the power mesh network to estimate voltage violations;6 Calculate the weighted cost function to obtain the current cost curr cost; 7 if curr cost ≥ init cost then Undo the block move;…”

mentioning

confidence: 99%

Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs

Chu

Xia

Wang

et al. 2013

2013 International Conference on Computer-Aided Design and Computer Graphics

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Multi-voltage technique is an effective way of power saving in system-on-a-chip (SoC) designs. However, as the technology nodes continue to shrink, the voltage drop constraint in multiple power domains presents serious obstacles in power/ground (P/G) network design of wire-bonding package. In this paper, a voltage drop aware power pad assignment and floorplanning method for multi-voltage SoC designs is proposed. In order to reduce the voltage drop, we develop a fast method to calculate the location of power pad for each power domain based on the spring model. During floorplanning iterations, a static voltage drop analysis is performed to update the voltage drop distribution, and then number of violation nodes in the P/G network is obtained. To speed up the floorplanning algorithm, instead of time-consuming matrix computation to obtain voltage drops, we use the weighted distance from blocks to power pads as an optimization objective. Experimental results on GSRC benchmark suites indicate that the proposed approach generates an optimized placement of power pads and floorplanning of blocks.

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SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems

Cited by 32 publications

References 38 publications

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

Irregularly shaped voltage islands generation with hazard and heal strategy

Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs

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