Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs

Abstract

In a multipower-mode design, as the range of the supply voltage becomes wide, a large clock skew may occur among different power domains. To remove this clock skew, conventional power-modeaware buffers (PMABs) require a large overhead on power consumption. In this brief, we propose a new PMAB architecture for wide-voltage-range multipower-mode designs. The proposed PMAB architecture is composed of two serially connected sub-PMABs at two different voltage levels, respectively. In the front sub-PMAB, the low voltage level is used for coarse-grained clock skew minimization. In the back sub-PMAB, the high voltage level is used for fine-grained clock skew minimization. Benchmark data show that the proposed approach can effectively eliminate the clock skew with small power consumption.

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

“…The Power Mode Aware Buffers (PMAB) removed the clock skew effectively. Chou et al [3] presented the new PMAB architecture with two sub-modules serially connected buffers under different voltage levels. The lowvoltage level was used to remove the clock skew in front side sub-PMA module and the high voltage level removed the clock skew problem in back side sub-PMAB.…”

“…1, 2 and 3 respectively. Table1 Wirelength analysis CKT Traditional Clustering DLWUC 1 23 18 2 25 21 3 26 20 4 26 23 5 21 19 6 20 15 7 19 13 8 17 14 9 21 17 10 15 11 Table 2 Channel width analysis CKT Traditional Clustering DLWUC 1 78 73 2 82 77 3 85 78 4 85 81 5 74 68 6 73 70 7 70 64 8 68 64 9 74 69 10 62 58 The circuits CKT1-CKT6 are created using the ISCAS'89 to validate the number of buffers requirement (Power Mode Aware Buffers (PMAB), Clock Buffers (CKB) and Delay Buffers(DLB)) [3]. The ISPD 2010 benchmark circuits used to validate the effectiveness of proposed algorithm over the existing obstacle avoiding [30], clustering-based Clock Tree Synthesis (CTS) models [28,29] .…”

“…The set of modules utilized to remove the clock skew under various power domains is called Power Mode Aware Buffers (PMAB) [3]. Based on the power modes, the supply voltage level is changed to assure the dynamic operation.…”