Skew-Oblivious Data Routing for Data Intensive Applications on FPGAs with HLS

Chen, Xinyu; Tan, Hongshi; Chen, Yao; He, Bingsheng; Wong, Weng-Fai; Chen, Deming

doi:10.1109/dac18074.2021.9586184

Cited by 5 publications

(2 citation statements)

References 20 publications

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“…However, real data streams are typically skewed, causing contention on some of the memory banks and, as a result, preventing meaningful performance gains. While there are some methods that have been proposed to reduce contention on the memory banks when processing has skewed streams [34,35], there is no efficient solution that guarantees a stall-free operation.…”

Section: Proposed Approach: Optimizations For Efficient Hardware Impl...mentioning

confidence: 99%

Finding the Top-K Heavy Hitters in Data Streams: A Reconfigurable Accelerator Based on an FPGA-Optimized Algorithm

Ebrahim

2023

Electronics

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This paper presents a novel approach for accelerating the top-k heavy hitters query in data streams using Field Programmable Gate Arrays (FPGAs). Current hardware acceleration approaches rely on the direct and strict mapping of software algorithms into hardware, limiting their performance and practicality due to the lack of hardware optimizations at an algorithmic level. The presented approach optimizes a well-known software algorithm by carefully relaxing some of its requirements to allow for the design of a practical and scalable hardware accelerator that outperforms current state-of-the-art accelerators while maintaining near-perfect accuracy. This paper details the design and implementation of an optimized FPGA accelerator specifically tailored for computing the top-k heavy hitters query in data streams. The presented accelerator is entirely specified at the C language level and is easily reproducible with High-Level Synthesis (HLS) tools. Implementation on Intel Arria 10 and Stratix 10 FPGAs using Intel HLS compiler showed promising results—outperforming prior state-of-the-art accelerators in terms of throughput and features.

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Section: Proposed Approach: Optimizations For Efficient Hardware Impl...mentioning

confidence: 99%

Finding the Top-K Heavy Hitters in Data Streams: A Reconfigurable Accelerator Based on an FPGA-Optimized Algorithm

Ebrahim

2023

Electronics

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“…Related work. Due to the diiculty in extracting enough parallelism at the compiling time, eicient HLS implementations still require hardware knowledge and signiicant development eforts; hence, a number of works improve the eiciency of HLS implementations [6,8,11,17,18,36,42,47,50,51,55,58,59]. Cong et al [17] proposed a composable architecture template to reduce the design space of HLS designs.…”

Section: Background and Related Work 21 Hls For Fpgasmentioning

confidence: 99%

ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS

Chen

Cheng

Tan

et al. 2022

ACM Trans. Reconfigurable Technol. Syst.

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FPGA has been an emerging computing infrastructure in datacenters benefiting from fine-grained parallelism, energy efficiency, and reconfigurability. Meanwhile, graph processing has attracted tremendous interest in data analytics, and its performance is in increasing demand with the rapid growth of data. Many works have been proposed to tackle the challenges of designing efficient FPGA-based accelerators for graph processing. However, the largely overlooked programmability still requires hardware design expertise and sizable development efforts from developers. ThunderGP , an HLS-based graph processing framework on FPGAs, is hence proposed to close the gap, with which developers could enjoy high performance of FPGA-accelerated graph processing by writing only a few high-level functions with no knowledge of the hardware. ThunderGP adopts the gather-apply-scatter (GAS) model as the abstraction of various graph algorithms and realizes the model by a build-in highly parallel and memory-efficient accelerator template. With high-level functions as inputs, ThunderGP automatically explores massive resources of multiple super-logic regions (SLRs) of modern FPGA platforms to generate and deploy accelerators, as well as schedule tasks for them. While ThunderGP on DRAM-based platforms is memory bandwidth bounded, recent high bandwidth memory (HBM) brings large potentials to performance. However, the system bottleneck shifts from memory bandwidth to resource consumption on HBM-enabled platforms. Therefore, we further propose to improve resource efficiency of ThunderGP to utilize more memory bandwidth from HBM. We conduct evaluation with seven common graph applications and nineteen graphs. ThunderGP on DRAM-based hardware platforms provides 1.9 × ∼ 5.2 × improvement on bandwidth efficiency over the state-of-the-art, while ThunderGP on HBM-based hardware platforms delivers up to 5.2 × speedup over the state-of-the-art RTL-based approach. This work is open-sourced on Github at https://github.com/Xtra-Computing/ThunderGP.

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