Skew-programmable clock design for FPGA and skew-aware placement

Abstract

In this paper, we propose a skew-programmable clock-routing architecture. The skews can be adjusted using programmable delay elements (PDEs) which we insert into the clock trees. We develop efficient, shortest-path-based algorithms for programming PDEs to optimize timing. Unlike previous methods for FPGA skew optimization which require large power and routing penalty, our method can achieve large timing improvement with small overhead. Typically, if timing requirements are tight, placers make efforts to satisfy them, often at a cost of compromising routability, total wire length, and power. In this work, we propose novel clockskew-aware placement algorithms which allow us to relax the timing constraints during placement. Timing can be later optimized as a post process. Even though we demonstrate the efficiency of our approach using FPGAs, the new skew optimization method and the new placement algorithm are quite general and can be applied to any general, topology-constrained skew optimization problem. Experimental results indicate that using the new clock-architecture we can obtain a 22% timing improvement for post-layout skew optimization and an additional 21% improvement from our skew-aware placement algorithm. In one fabric, the cost of added logic is 2.19% as measured by dynamic power dissipation, and 0.85% in terms of area overhead.

Statistical Generic and Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs

“…From the figure we can see that most of the failing chips fall in the bins (0,1] and (1,2]. Furthermore, about 88% of failed chips fall in the extended delay bin (0,5]. This indicates that we can correct a lot of timing violations if we can reduce the delay on critical paths of circuits by even a small amount.…”

“…This approach incurs substantial power and routing overhead. In [5], the authors proposed a new clock-routing architecture consisting of a global H-tree and a local spineand-ribs structure. They inserted PDEs on alternate branch points of the global H-trees to distribute skews.…”

Latch-Based Performance Optimization for FPGAs

“…Other work [10], [11] involving FPGAs has focused on the use of programmable delay elements (P DEs) to purposely delay clock signals. The work in [10] used PDEs on the clock tree, whereas the PDEs were inserted into FPGA logic elements in [11].…”

“…The work in [10] used PDEs on the clock tree, whereas the PDEs were inserted into FPGA logic elements in [11]. Both methods incur a hardware penalty and require additional architectural considerations.…”

“…We can relax this non-linear constraint by first transforming (10) to occur between every latch pair connected by a combinational path. We conservatively assume that every early signal launches at the beginning of a latch's opening window (i.e.…”