Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems

Abstract

We present a bus arbitration scheme for soft real-time constrained embedded systems. Some masters in such systems are required to complete their work for given timing constraints, resulting in the satisfaction of system-level timing constraints. The computation time of each master is predictable, but it is not easy to predict its data transfer time since the communication architecture is mostly shared by several masters. Previous works solved this issue by minimizing the latencies of several latency-critical masters, but the side effect of these methods is that it can increase the latencies of other masters, hence they may violate the given timing constraints. Unlike previous works, our method uses the concept of "slack" in order to make the latency as close as its given constraint, resulting in the reduction of the side effect. The proposed arbitration scheme consists of bandwidth-conscious arbiter and scheduler. The arbiter can be any existing bandwidth-conscious arbiter and the scheduler implements the latency-awareness proposed in this paper. The scheduler is involved in the arbitration only when it observes a request whose slack is not sufficient for the given timing constraint. The experimental results show that our method outperforms the conventional round-robin arbiter by more than 100% in the best case in terms of the longest violated cycles.

Designing of a AMBA-AHB Multilayer Bus matrix SelfMotivated Arbitration scheme

“…The computation time of each master is predictable, but it is not easy to foresee the data transfer time since the on-chip bus is usually shared by several masters. Previous works solved this issue by minimizing the la-tencies of several latencycritical masters, but a side effect of these methods is that they can increase the latencies of other masters; hence, they may violate the given timing constraints [16]. Unlike existing works, our scheme can keep the latency close to its given constraint by adjusting the priority level and transfer length of the masters.…”

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

“…Adaptations for the memory controller have been proposed by Mirosanlou et al (2020), Hassan et al (2017), Valsan and Yun (2015), Akesson et al (2007) andFernandez-De-Lecea et al (2023) to reduce the worst-case latency of memory requests under multicore contention. Time Division Multiplexing hardware implementations have also been proposed by Hebbache et al (2018), Jun et al (2007, and Li et al (2016) and Kostrzewa et al (2016) to improve predictability of the memory interconnect level. On MPSoCs (e.g.…”

Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning

“…Several works have been proposed to improve the bandwidth and latency of the shared bus architecture by employing sophisticated arbitration schemes [16][17][18] and by physically segmenting the bus to enable concurrent communications [19,20]. Medardoni et al [21] analyzed the effect of the protocol, bridge design and traffic pattern on the hierarchical bus architecture and Drinic et al [22] proposed the automated design method for hierarchical bus architecture.…”