Slew-Rate Enhancement of a Full-On Chip CMOS LDO Based on a Capacitorless Push–Pull Current Booster Circuit

A capacitorless low dropout (LDO) voltage regulator with a dynamic enhancement slewrate (DESR) has been presented in this chapter. A new technique based on the active component in CMOS technology has been designed, studied, and integrated on the full-on chip proposed LDO. The proposed technique was designed as a dynamic detection of LDO output voltage variation due to the load current variation or supply voltage variation. The proposed architecture has been simulated in TSLC 0.18μm CMOS process. The settling time of the load regulation response is 1 us with undershoot of 0.44mV/mA for the load capacitance of 100 pF. the results simulation shows that the proposed system is stable under full load (50” ” mA) and no load (0” ” mA) current with phase margin of 76^∘.

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Slew-Rate Enhancement of a Full-On Chip CMOS LDO Based on a Capacitorless Push–Pull Current Booster Circuit

Cited by 3 publications

References 12 publications

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