Small signal and HF noise performance of 45 nm CMOS technology in mmW range

Abstract

The development of applications in millimeter wave range (mmW) during the last decade is strongly related to continuous progress of Si Technology, which kept on evolving through aggressive transistor gate length down-scaling. In this context, this paper aims to present DC, small signal and noise performance up mmW range of recently developed 45-nm bulk CMOS Technology. For this purpose, S parameters were measured up to 67 GHz, a high frequency (HF) noise model was extracted in 6-40 GHz frequency range, and its accuracy verified through a comparison with the noise figure measured in W band with a 50 Ω impedance set at the transistor. The technology offers f T , f MAX respectively of 200 and 300 GHz in line with up-to-date published results for a 45 nm CMOS Technology. At the meantime, a minimum noise figure of 4.5 dB at 94 GHz is demonstrated (verified through W band noise measurements).Index Terms -Millimeter wave measurement, CMOS 45nm, Sparameters, small signal model, noise model.

Modeling of high‐frequency noise of silicon CMOS transistors for RFIC design

“…In this work, we present a detailed analysis of high‐frequency noise of a 90‐nm CMOS process, which still retains industrial interest, because of its high RF‐performance‐to‐cost ratio . In recent publications, RF noise has been modeled with respect to frequency, bias and scaling . However, models are often incomplete, either due to limitations in the measured frequency , or due to limitations in the measured geometries .…”

“…However, models are often incomplete, either due to limitations in the measured frequency , or due to limitations in the measured geometries . Even when these areas are thoroughly covered, NF min is not shown over bias , and the thermal noise excess factor, which is an important design quantity for RF LNAs, is either not adequately presented, or not presented at all .…”

CMOS RF noise, scaling, and compact modeling for RFIC design

“…Scaling CMOS to the deca-nanometer regime, a tremendous improvement of RF performance has been reported in terms of conventional figures of merit (FoM), such as f T and f max [1]- [2]. However, a large amount of industrial IC design of RF front ends is still done using CMOS technology nodes such as 180 nm and 90 nm, due to their high RF-performance-to-cost ratio [3].…”

Optical high frequency test structure and test bench definition for on wafer silicon integrated noise source characterization up to 110 GHz based on Germanium-on-Silicon photodiode

“…This extraction is realized on wafer and modeled down to sub-millimeter wave range. Nevertheless, there are no commercial noise sources available over 170 GHz, avoiding the use of traditional characterization bench for noise parameters determination [1], [2]. An alternative solution could be the use of photodiode as white noise generator [3].…”