Small-signal MOSFET models for analog circuit design

Liu, S.; Nagel, Laurence W.

doi:10.1109/jssc.1982.1051852

Cited by 97 publications

(12 citation statements)

References 25 publications

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“…Also, it should be recognized that for these simulations Spice2G6 level II was used. The limitations in the transistor model of this version are very well known [ 4,6,7,33] The measured hannonic distortion components are shown in Fig. 3.2.…”

Section: Practical Limitations Of Ot a Based Integratorsmentioning

confidence: 99%

“…In the most general case the transistor conductance is mainly due to both effects channel length modulation and drain-induced barrier lowering. The output conductance of the MOS transistor can be approximated by[4,6,33] (3 30). where Is, L and vo are the drain bias current, the effective length of the gate and the ac output voltage, respectively.…”

mentioning

confidence: 99%

“…kappa and Early voltage (in VI J..Lm), are Spice fitting parameters. Detailed definitions of these parameters can be found in the references[4,6,7,33]. The voltage Vx is given by(3.32) with Vos the drain-source bias voltage.…”

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confidence: 99%

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Design Considerations for OTA-C Integrators and Full CMOS Resistors

Silva-Martínez

Steyaert

Sansen

1993

High-Performance CMOS Continuous-Time Filters

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In the earlier generation of continuous-time filters the basic network elements were the inductor, the capacitor and the resistor. With the evolution of the Integrated Circuits (IC), however, the inductors have been replaced by equivalent networks composed of active devices and capacitors. The resulting topologies are called Active RC filters. The active devices of the active RC filters are either OP AMPs or OT As, see Fig. 1.1 (chapter 1). For high-frequency applications the OTA based circuits have been preferred.For IC filters, the integrator is the basic block. The lossless integrator consists of a voltage-to-current converter and of the integrating capacitor. The voltage-tocurrent converter can be implemented using a resistor and the virtual ground of an OPAMP with local feedback. The other possible implementation is using linear voltage-to-current converters, OT As. In this text we are only interested in the second technique. In particular, in this chapter the lossless integrator and the lossy integrator and the full CMOS resistors are further discussed.The OT A based continuous-time 1ossless integrator is composed by an OT A and a capacitor. In the previous chapter, the voltage-to-current converter has been discussed in detail. In this chapter, in section 3.2 the noise level of the full OT A is explored. In CMOS technologies, the capacitors are implemented as poly-silicon capacitors [1-3]. However, due to the lack of virtual grounds of the OTA based continuous-time filters, the behavior of the signal processor is affected by the parasitic capacitors. The effects of those parasitic capacitors are further discussed. In that section, it is demonstrated that the non-linearities of the bulk capacitors can produce high harmonic distortions. If the junction capacitors are comparable to the poly-silicon capacitors then these harmonic distortions are even higher than the harmonic distortions due to the OT A non-linearities. Based on the analysis of both load J. Silva-Martínez et al., High-Performance CMOS Continuous-Time Filters

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Section: Practical Limitations Of Ot a Based Integratorsmentioning

confidence: 99%

mentioning

confidence: 99%

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Design Considerations for OTA-C Integrators and Full CMOS Resistors

Silva-Martínez

Steyaert

Sansen

1993

High-Performance CMOS Continuous-Time Filters

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“…MECCA (Characterization) is the procedure used to generate parameter files for use in the circuit simulator ADVICE. If the technology is CMOS, for example, ASIM [11] ( Figure 5) and CSIM [12] parameter files are generated. As seen in Figure 4, the work horses of this system are BICEPS-5.0, for process simulation, MEDUSA, for device simulation, and a variety of parameter extraction and data reduction tools, such as ASIMPAC [11], MOSPAC [12], ARTHUR and PAREX [13].…”

Section: 11 Mecca For Technology Characterizationmentioning

confidence: 99%

Technology CAD for competitive products

Lloyd

Dirks

Prendergast

et al. 1990

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Recent trends in the integration of process, device and circuit modeling tools and the current rapid emergence of UNIX® based computing environments of networked workstations and compute engines makes possible user-friendly, taskbased CAD systems for technology optimization, characterization and cell design. The paper discusses these trends and identifies opportunities to leverage Technology CAD tools in the development of competitive technologies and products. i I:This paper describes how tools for technology CAD, in use at AT&T Bell Laboratories, arc integrated into a task-based system designed to meet the needs of IC technology development and circuit design for optimization, characterization, and verification. TCAD is the name given to this system and it is made up of state-of-the-art, user-friendly modeling tools. These tools include those for process, device and circuit simulation, parameter extraction and optimization.The TCAD environment is UNIX. The highest level of TCAD is a user interface program, tcad, written in C and shell, tcad is easily ported across UNIX systems so the investment in development is protected and efforts are not duplicated. It monitors access and usage patterns, tracks tasks routinely performed, has electronic communication facilities between users and program developers and provides various levels of restricted-access for certain sensitive or beta-stage tools and technology files. Provision is made to capture input files to add to the regression data-base, or when tools terminate abnormally. TCAD tools can be used independently or coupled together to form tasks.The TCAD system is open to the integration of a variety of tools including exploratory products and the primary TCAD tools are accurate, flexible, robust and user-friendly. Some of these primary tools are described in the next section. The philosophy behind the TCAD architecture is outlined in the third section. Much of the power of TCAD comes from UNIX through networking and distributed computing. These features of UNIX and their impact on TCAD arc described in Section 4. Several examples of TCAD tasks and concluding remarks are given in the fifth and sixth sections, respectively. The Building Blocks for TCADTCAD leverages current predictive tools for process to cell level design. Some of these tools are described below including the process simulator BICEPS-5.0, the device simulator MEDUSA, the statistical process/device simulator FABRICS, the parameter extractor ARTHUR, the circuit simulator ADVICE and the optimizer CENTER. The Process Simulator BICEPS-5.0BICEPS-5.0 is a modular two-dimensional process simulator that retains the coordinate transformation philosophy of the original code [4]. It contains models for ion implantation, predeposition, drive-in in inert and oxidizing ambients, epitaxy, etching and deposition. The diffusion equation is solved using finite differences. Improvements over the original code include new physical models, an improved user interface, a new graphic package and new numerical methods.The i...

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“…To achieve analytical relationships between the pole-zeros and the small-signal device parameters: the post-amplifier M l -M 7 is presented by a simplified circuit and its smallsignal model [7] circuit is shown in Fig. 2.…”

Section: B 1 Ideal Analysismentioning

confidence: 99%

A 100 MHz synchronized OEIC photoreceiver in n-well, CMOS technology

Ayadi

Danielsen

1998 Conference on Optoelectronic and Microelectronic Materials and Devices. Proceedings (Cat. No.98EX140)

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Abstruct-We analyze and demonstrate a synchronized CMOS photoreceiver for the conversion of optical inputs of pulse-light to electronic digital signals. Small-signal and photonic analysis of the proposed circuit are detailed. The photoreceiver was operated at 100 MHz with only 13.3 fJ/pulse of 830-nm input light. Its effective area is 100 x 60 pm2 which makes this monolithic photoreceiver extremely important for use in data storage and optical interconnection applications.

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Small-signal MOSFET models for analog circuit design

Cited by 97 publications

References 25 publications

Design Considerations for OTA-C Integrators and Full CMOS Resistors

Design Considerations for OTA-C Integrators and Full CMOS Resistors

Technology CAD for competitive products

A 100 MHz synchronized OEIC photoreceiver in n-well, CMOS technology

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