Small-signal parameters extraction and noise analysis of CNTFETs

Abstract

The use of carbon nanotube (CNT) field-effect transistors (FETs) in microwave circuit design requires an appropriate, immediate and efficient description of their performance. This work describes a technique to extract the parameters of an electrical equivalent circuit for CNTFETs. The equivalent circuit is used to model the dynamic and noise performance at low-and highfrequency of different CNTFET technologies, considering extrinsic and intrinsic device parameters as well as the contact resistance. The estimation of the contact resistance at the metal/CNTs interfaces is obtained from a Y-function based extraction method. The noise model includes four noise sources: thermal noise, thermal channel noise, shot channel noise and flicker noise. The proposed model is compared with a compact model calibrated to hysteresis-free experimental data from a high-frequency multi-tube (MT)-CNTFET technology. Additionally, it has been applied to experimental data from another fabricated MT-CNTFET technology. The comparison in both cases shows a good agreement between reference data (simulation and experimental) and results from the proposed model. Low-and high-frequency noise projections of the fabricated reference device are further studied. Noise results from both studied technologies show that shot noise mainly contributes to the total noise due to the presence of Schottky barriers at contacts and along the channel.

A Small-Signal Description of Black-Phosphorus Transistor Technologies for High-Frequency Applications

“…Drain and source contact resistances, R dc and R sc , respectively, have been included in the intrinsic device model since they can not be removed with standard de-embedding techniques: they embrace the contribution of bias-dependent potential barriers at the interfaces of the BP channel and the metallic contacts [9]- [11]. Their contribution can be mathematically removed however, if experimental S-parameters are available [12], [13]. Intrinsic electrostatics couplings are represented by the gate-to-source/gateto-drain/drain-to-source capacitance C gs/gd/ds .…”

“…The intrinsic transistor is within the dashed box using the approach presented in [19]. Model parameters for the T 1 500 nm-long device [3] have been extracted using a proper detachment of R dc/sc [12], [13] enabled by available experimental S-parameters. For the other devices, S-parameters data are not available and hence, the parameters extraction is as follows.…”

A small-signal GFET equivalent circuit considering an explicit contribution of contact resistances

“…Non-negligible device contact resistances have been considered in this EC. This approach has been useful as well for small-signal EC describing the HF performance of other emerging transistors [13] and it has been followed for the first time in GFETs here. The intrinsic elements are between the g i , s i and d i nodes.…”

“…In the context of graphene devices in general, the contact resistances R sc/dc embrace both external and internal device phenomena [9]- [12] and their impact on the intrinsic device performance can not be separated by standard de-embedding procedures. The extraction of the small-signal parameters used here has been introduced elsewhere [13] for a different low-dimensional transistor technology. This methodology is applied in this work to two GFET technologies and it is summarized as follows.…”

“…The HF characterization of a pad dummy structure yields an admittance matrix Y pad from which the inner-parasitic capacitances (C gsp2/gdp2/dsp2 ) are obtained. The de-embedded admittance matrix Y dem of the device 1 , including the impact of R c , is related to the raw extrinsic admittance matrix Y raw by using Y open , Z short and Y pad in a three-step parasitic de-embedding method [13], [14].…”