SmarCo: An Efficient Many-Core Processor for High-Throughput Applications in Datacenters

Fan, Dongrui; Li, Wenming; Ye, Xiaochun; Da, Wang; Zhang, Hao; Tang, Zhimin; Sun, Ninghui

doi:10.1109/hpca.2018.00057

Cited by 15 publications

(6 citation statements)

References 32 publications

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“…In October 2018, the Institute of Computing Technology, Chinese Academy of Sciences (ICT) launched the first High-Throughput computer at the China National Computer Congress (CNCC). High-throughput computer is integrated with a series of innovative technologies of ICT, including High-throughput many-core architecture (Fan et al 2018), High-Throughput on-chip data paths and Labeled von Neumann Architecture (Dongrui et al 2019). Each processing core adopts variable-length pipeline and multi-transmission structure, which significantly improves the instruction throughput efficiency.…”

Section: High Throughput Clustersmentioning

confidence: 99%

Scalable and efficient graph traversal on high-throughput cluster

et al. 2020

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Section: High Throughput Clustersmentioning

confidence: 99%

Scalable and efficient graph traversal on high-throughput cluster

et al. 2020

Self Cite

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“…processor consists of processing elements (PEs), data buffers (Dbufs), instruction buffers (Cbufs), a micro-controller unit (MicC), and a DMA controller. The structure of SPU is similar to traditional many-core architectures (Fan et al 2012(Fan et al , 2018 but every PE inside the array is a fine-grained dataflow processing element not a control-flow core. The Dbufs and Cbufs are implemented by using Scratch-Pad Memory (SPM).…”

Section: Spu Structurementioning

confidence: 99%

Applying CNN on a scientific application accelerator based on dataflow architecture

Xiang

et al. 2019

CCF Trans. HPC

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Convolutional neural network (CNN) is widely used in applications such as face recognition, intelligent monitoring, image recognition and text recognition. Because of its high computational complexity, many efficient hardware accelerators have been proposed to exploit high degree of parallel processing for CNN. However, accelerators which are implemented on FPGAs and ASICs usually sacrifice generality for higher performance and lower power consumption. Other accelerators, such as GPUs, are general enough, but they lead to higher power consumption. Fine-grained dataflow architectures, which break conventional Von Neumann architectures, show natural advantages in processing scientific applications. Meanwhile, CNN algorithm shares many vital characteristics with scientific applications including high parallelism, simple loop and regular memory accessing pattern. In this paper, we propose a scheme for implementing and optimizing CNN on fine-grained dataflow architecture designed for scientific applications, namely Scientific Processing Unit (SPU). The experiment results reveal that by using our scheme, the performance of AlexNet and VGG-19 running on SPU is averagely 2.29 × higher than that on NVIDIA Titan Xp, and the energy consumption of our hardware is averagely 5.76 × lower than that of Titan Xp.

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“…There are several reasons that cause high memory access latency in convolution operations. In the case of DDR memory type, the main methods of reducing the latency of memory access problems of convolutional operations include increasing the utilization rate of on-chip buffer resources [11] [12], using more off-chip memory [13] [14] or improving the utilization of off-chip memory [12], etc.…”

Section: Introductionmentioning

confidence: 99%

OptTc: A method of optimizating memory access latency for convolutional accelerators

Zhao,

Wang,

Zhang

et al. 2023

Preprint

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SmarCo: An Efficient Many-Core Processor for High-Throughput Applications in Datacenters

Cited by 15 publications

References 32 publications

Scalable and efficient graph traversal on high-throughput cluster

Scalable and efficient graph traversal on high-throughput cluster

Applying CNN on a scientific application accelerator based on dataflow architecture

OptTc: A method of optimizating memory access latency for convolutional accelerators

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