Smart cache: A self adaptive cache architecture for energy efficiency

Abstract

Abstract-The demand for low-power embedded systems requires designers to tune processor parameters to avoid excessive energy wastage. Tuning on a per-application or per-applicationphase basis allows a greater saving in energy consumption without a noticeable degradation in performance. On-chip caches often consume a significant fraction of the total energy budget and are therefore prime candidates for adaptation.Fixed-configuration caches must be designed to deliver low average memory access times across a wide range of potential applications. However, this can lead to excessive energy consumption for applications that do not require the full capacity or associativity of the cache at all times. Furthermore, in systems where the clock period is constrained by the access times of level-1 caches, the clock frequency for all applications is effectively limited by the cache requirements of the most demanding phase within the most demanding application. This results in both performance and energy efficiency that represents the lowest common denominator across the applications.In this paper we present a Set and way Management cache Architecture for Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 14% better than state-of-the-art cache reconfiguration architectures. We then leverage the flexibility provided by our cache to dynamically reconfigure the hierarchy as a program runs. We develop a decision tree based machine learning model to control the adaptation and automatically reconfigure the cache to the best configuration. Results show an average reduction in energy-delay product of 17% in the data cache (just 1% away from an oracle result) and 34% in the level-2 cache (just 5% away from an oracle), with an overall performance degradation of less than 2% compared with a baseline statically-configured cache.

Superoptimization of memory subsystems

“…Methods to change the size and associativity of a cache hierarchy dynamically have been explored [2,29] and the ability to disable various levels of a multi-level cache in the interest of reducing latency and reducing power consumption has been considered [5]. Finally, adjusting the size of cache lines dynamically to lower the cache miss rate has been considered [31].…”

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

“…We have proposed a configurable cache architecture that allows reconfiguration of both the size and associativity of each cache, providing maximum flexibility to the application [28]. We have compared our approach, called the Smart cache, against state-of-the-art cache reconfiguration techniques and showed that our scheme's energy-delay product is on average 14% better than these prior works.…”

“…-We have extended the previous work [28] to multicore systems and evaluated both two-core and four-core systems. This is an important extension, as the cores compete for the Last Level Cache (LLC), their memory access pattern changes, making it difficult to predict the right cache size and associativity for the LLC.…”

“…-We compared both prediction models based on decision trees and linear regression. In [28], a decision tree based prediction model is used. However comparing it with a well known other prediction model gives the merit and hardware feasibility of decision trees.…”

Otimização de memória cache em tempo de execução para o processador embarcado LEON3

“…Com base neste contexto, elaborar alguma técnica que aperfeiçoe a cache de instruções e de dados de acordo com a necessidade da aplicação em execução, de maneira que este processo seja realizado em tempo de execução, pode resultar em reduções expressivas no consumo de energia do sistema. Está técnicaé conhecida como reconfiguração dinâmica da cache (Sundararajan et al, 2011). Com a técnica pode-se ainda reduzir o miss rate da cache e como consequência melhorar o desempenho da aplicação em execução.…”