Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding^*1

Abstract

An alternative route to existing silicon on insulator (SOI) material technologies such as SIMOX (separation by implanted oxygen) and BESOI (bonded and etch-back SOI) is the new Smart-Cut process, which appears to be a good candidate to achieve ULSI criteria. The Smart-Cut process involves two technologies: wafer bonding and ion implantation associated with a temperature treatment which induces a in-depth splitting of the implanted wafer. The details of the Smart-Cut process, the physical phenomena involved in the different technological steps such as hydrogen implantation related mechanisms and wafer bonding are discussed. The characteristics of the final structure in terms of thickness homogeneity, crystalline defects, surface microroughness, and electrical characterization are presented. Other applications of this process are also highlighted.

Thin crystalline silicon solar cells based on epitaxial films grown at 165°C by RF-PECVD

“…Moreover, by using an SiF 4 plasma etching step on the wafer substrate before deposition, we have found that it is possible to produce a crystalline silicon layer having a porous interface with the crystalline silicon wafer, which allows to easily detach the epitaxial film from the substrate [8,9]. In this way it is possible to produce thin and flexible crystalline silicon wafers that could be used for electronic devices, in a similar way to the "smart-cut" process [10]. Last but not least, we have also shown that it is possible to grow doped epilayers and produce in this way efficient p-n junction solar cells [11].…”

Hydrogen Interaction with Dislocations in Si

“…Firstly, because the effect is large, reducing the activation energy for motion by 1 eV, and, secondly, because our understanding of H in Si is crucial to the "smart-cut" process for silicon-on-insulator technology [13].…”

Fabrication of 3D Photonic Crystals toward Arbitrary Manipulation of Photons in Three Dimensions

“…Therefore, we considered the influence of the strain energy in bonded SOI/SOI structures to obtain uniform bonding at room temperature. Here, SOI wafers generally possess warpage owing to their fabrication process; the SOI structure is typically fabricated by bonding Si and SiO 2 (or SiO 2 and SiO 2 formed on Si) at high temperatures such as 1400 K [41], and the internal stress is accumulated and warpage is induced at room temperature owing to the difference between the thermal expansion coefficients of Si and SiO 2 . Figure 7 shows the calculated effective strain energy of bonded SOI/SOI structures with several thicknesses of the buried SiO 2 layer and handle Si substrate.…”