Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Ghosh, Mrinmoy; Lee, Hsien-Hsin S.

doi:10.1109/micro.2007.4408251

Cited by 47 publications

(92 citation statements)

References 14 publications

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“…RELATED WORK Refresh Reduction. Ghosh et al [22] proposed Smart Refresh to eliminate unnecessary refresh operations. It leverages the characteristics that a read/write is equivalent to refresh due to the destructive access.…”

Section: Four-core Simulation Resultsmentioning

confidence: 99%

Alleviating DRAM Refresh Overhead Via Inter-rank Piggyback Caching

Guo

Huang

Young

et al. 2015

2015 IEEE 23rd International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems

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DRAM cells leak charge over time, causing stored data to be lost. Therefore, periodic refreshes are required to ensure data integrity. Modern DRAM usually refreshes cells at rank level, resulting in an entire rank being unavailable during a refresh period. As DRAM density keeps increasing, more rows need to be refreshed during a single refresh operation, which causes higher refresh latency and significantly degrades the overall memory system performance.To mitigate DRAM refresh overhead, we propose a caching scheme, called Rank-level Piggyback Caching, or RPC for short, based on the fact that ranks in the same channel are refreshed in a staggered manner. The key idea is to cache the to-be-read data in a rank (e.g. Rank 1) to its adjacent rank (e.g. Rank 2) before Rank 1 is locked for refresh. Each rank reserves or over-provisions a very small area, denoted as a cache region, to store the cached data. The cache regions from all ranks are organized in a rotated fashion. In other words, the cached data for the last rank is stored in the first rank. When a read request arrives at a rank undergoing refresh, the memory controller first checks the cache region in the next rank in the same channel; if the requested data is cached, the memory controller services the request from the cache without waiting for the refresh operation to complete, which reduces memory access latency and improves system performance.Our experimental results show that RPC outperforms existing Fine Granularity Refresh modes. In a single-core and four-rank system, it improves system performance by 8.7% and 10.8% on average for the PARSEC 2.1 and SPLASH-2 benchmark suites, respectively. In a four-core and four-rank system, the improvement of system performance for these two benchmark suites is 8.6% and 12.2%, respectively.

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Section: Four-core Simulation Resultsmentioning

confidence: 99%

Alleviating DRAM Refresh Overhead Via Inter-rank Piggyback Caching

Guo

Huang

Young

et al. 2015

2015 IEEE 23rd International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems

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show abstract

“…This consists of 24.9% of the DRAM power. Many prior work has been proposed to reduce the Background Power [16,17,18,19,20] or RD/WR/Termination Power [21,22]. In this paper, our focus is on the minimization of the Activation Power.…”

Section: Dram Preliminarymentioning

confidence: 99%

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation

Zhang

Chen

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

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DRAM memory is a major contributor for the total power consumption in modern computing systems. Consequently, power reduction for DRAM memory is critical to improve system-level power efficiency. Fine-grained DRAM architecture [1,2] has been proposed to reduce the activation/precharge power. However, those prior work either incurs significant performance degradation or introduces large area overhead. In this paper, we propose a novel memory architecture Half-DRAM, in which the DRAM array is reorganized to enable only half of a row being activated. The half-row activation can effectively reduce activation power and meanwhile sustain the full bandwidth one bank can provide. In addition, the half-row activation in Half-DRAM relaxes the power constraint in DRAM, and opens up opportunities for further performance gain. Furthermore, two half-row accesses can be issued in parallel by integrating the sub-array level parallelism to improve the memory level parallelism. The experimental results show that Half-DRAM can achieve both significant performance improvement and power reduction, with negligible design overhead.

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“…Hur and Lin study the power saving potential of a memory scheduling scheme and evaluates a scheme to predict throttling delay for memory power control [10]. Ghosh et al propose adaptive refresh method to reduce the refresh power [8]. The decoupled DIMM improves memory power efficiency in a different way by allowing DRAM devices to run at a relatively low data rate.…”

Section: Related Workmentioning

confidence: 99%

Decoupled DIMM

Zheng

Jiang

Zhang

et al. 2009

SIGARCH Comput. Archit. News

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The widespread use of multicore processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. In a conventional DDR2/DDR3 DRAM memory system, the memory bus and DRAM devices run at the same data rate. To improve memory bandwidth, we propose a new memory system design called decoupled DIMM that allows the memory bus to operate at a data rate much higher than that of the DRAM devices. In the design, a synchronization buffer is added to relay data between the slow DRAM devices and the fast memory bus; and memory access scheduling is revised to avoid access conflicts on memory ranks. The design not only improves memory bandwidth beyond what can be supported by current memory devices, but also improves reliability, power efficiency, and cost effectiveness by using relatively slow memory devices. The idea of decoupling, precisely the decoupling of bandwidth match between memory bus and a single rank of devices, can also be applied to other types of memory systems including FB-DIMM.Our experimental results show that a decoupled DIMM system of 2667MT/s bus data rate and 1333MT/s device data rate improves the performance of memory-intensive workloads by 51% on average over a conventional memory system of 1333MT/s data rate. Alternatively, a decoupled DIMM system of 1600MT/s bus data rate and 800MT/s device data rate incurs only 8% performance loss when compared with a conventional system of 1600MT/s data rate, with 16% reduction on the memory power consumption and 9% saving on memory energy.

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Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Cited by 47 publications

References 14 publications

Alleviating DRAM Refresh Overhead Via Inter-rank Piggyback Caching

Alleviating DRAM Refresh Overhead Via Inter-rank Piggyback Caching

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation

Decoupled DIMM

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