SMASHUP: a toolchain for unified verification of hardware/software co-designs

Abstract

Critical and privacy-sensitive applications of smart and connected objects such as health-related objects are now common, thus raising the need to design these objects with strong security guarantees. Many recent works offer practical hardware-assisted security solutions that take advantage of a tight cooperation between hardware and software to provide system-level security guarantees. Formally and consistently proving the efficiency of these solutions raises challenges since software and hardware verifications approaches generally rely on different representations. The paper first sketches an ideal security verification solution naturally handling both hardware and software components. Next, it proposes an evaluation of formal verification methods that have already been proposed for mixed hardware/software systems, with regards to the ideal method. At last, the paper presents a conceptual approach to this ideal method relying on ProVerif, and applies this approach to a remote attestation system (SMART).

A Survey of Cybersecurity Certification for the Internet of Things

“…A full or partial resolution of this problem could facilitate the cybersecurity certification of complex IoT system on the basis of the certification and labelling of the single components. In this direction, the use of hardware-software co-verification methods could be considered as part of the overall certification process of composed devices or systems [114]. However, these techniques need to be further analyzed in the coming years to check their suitability in the context of IoT.…”

Remote Attestation of Bare-Metal Microprocessor Software: A Formally Verified Security Monitor

“…They dedicated a protected memory region to store the secret. Lugou et al [10] tried to propose a unified method to verify hardware/software co-designs. They applied this method on SMART and modelled the system with Proverif.…”

Formal Techniques for Effective Co-verification of Hardware/Software Co-designs

“…Figure 4 and Figure 5 gives the properties under verification. Column [1][2][3][4][5][6][7][8][9][10][11][12] in Table 1 report the property id, type of property, the bound up to which the HW transition system is unwound, the unwind depth for the SW, number of SAT clauses, number of variables, the verification result (safe or unsafe), the source of the bug (HW or SW or Interface logic) if unsafe, and the total verification run time and memory consumption for bit-level and word-level backend solvers, respectively. Note that the value of bound must be greater or equal to the number of next_time f rame() calls.…”

“…The work of [8,17] concerns co-verification for the case of an RTL HW. Unified high-level HW/SW models for co-verification have been pursued in the past [9]. Notably, Monniaux [11] model HW and SW as C programs, which are formalized as pushdown systems (PDS), Li et al [8] use Büchi Automata to model HW and a PDS to model SW to generate a unified model, called Büchi Pushdown System (BPDS).…”