Smoothing based fast model for images of isolated buried EUV multilayer defects

Abstract

A new fast-CAD imaging model for buried extreme ultra violet (EUV) mask defects is presented that exploits the smoothing process used to mitigate buried EUV multilayer defects. Since the characteristics of the smoothing process dictate nearly identical surface shapes for all defects a single parameter, the peak height of the final profile, is sufficient to predict the projection printed image for an arbitrary buried defect. Data is presented on the effect of smoothing on the reflected field and final wafer image. The degree of similarity among defects with different initial heights, widths and shapes is explored. A compact algebraic model to predict the aerial image dip strength is developed that depends only on the surface height of the EUV mask blank. This model is then integrated into a standard perturbation model for defect feature interaction, and the importance of accounting for absorber features shadowing of buried defects is demonstrated.

Defect-aware reticle floorplanning for EUV masks

“…We use a simple pessimistic linear model for critical dimension (CD) impact of buried defects that was proposed by Clifford et. al [10]. We use the same image slope and fitting constants.…”

“…This assumption is reasonable due to smoothing process during multi-layer deposition [10]. As shown in Figure 2, H is the maximum height of the gaussian defect and full width half maximum (FWHM) is the width of the defect where height is H/2.…”

New yield-aware mask strategies

“…Clifford et al 10 show that square defects at the substrate with widths varying from 60nm to 90nm all result in around 50-60nm defect widths at the final multi-layer (ML) surface, and that defect heights can vary from 1.5nm to 5.5nm. Critical dimension (CD) varies mainly with the defect height at the top of the ML surface; Clifford et al also propose a simple linear equation to calculate CD variation (ΔL) from the surface defect height as…”

“…Table 6 summarizes the defect heights assumed in our experiments, and their respective impacts on CD and timing. To calculate ΔL, we use Equation (2) with the same parameters used by Clifford et al 10 † To quantify the impact on timing, we measure delay variation (ΔT ) from a nominal worst-case delay of a most frequently used cell (i.e., 2-input NAND gate) in our testcase with respect to transistor gate length, using a 45nm open-source design kit. 12 From the delay variation due to defects, we can estimate parametric yield.…”

“…For this experiment, other parameters are fixed in a reasonable ranges. Defect height is assumed as 4nm and defect influence distance is assumed as 30nm in wafer (120nm in reticle), which is 2× a typical FWHM reported by Clifford et al 10 Defects are assumed to have a uniform random distribution. Figure 8 compares parametric yields of various reticle strategies.…”