SMT-Based System Verification with DVF

Automated Deduction – CADE-24

Goel

et al. 2013

Self Cite

Abstract. SMT-based applications increasingly rely on SMT solvers being able to deal with quantified formulas. Current work shows that for formulas with quantifiers over uninterpreted sorts counter-models can be obtained by integrating a finite model finding capability into the architecture of a modern SMT solver. We examine various strategies for on-demand quantifier instantiation in this setting. Here, completeness can be achieved by considering all ground instances over the finite domain of each quantifier. However, exhaustive instantiation quickly becomes unfeasible with larger domain sizes. We propose instantiation strategies to identify and consider only a selection of ground instances that suffices to determine the satisfiability of the input formula. We also examine heuristic quantifier instantiation techniques such as E-matching for the purpose of accelerating the search. We give experimental evidence that our approach is practical for use in industrial applications and is competitive with other approaches.

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Section: Resultsmentioning

confidence: 99%

Quantifier Instantiation Techniques for Finite Model Finding in SMT

Automated Deduction – CADE-24

Goel

et al. 2013

Self Cite

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“…A new vertex from the region is added to this set whenever two vertices in it are merged, to maintain the set's size at k + 1. 9 The solver also keeps track of all pairs of watched vertices that are not linked. This way it knows that the region contains a (k + 1)-clique as soon as the set of those pairs becomes empty.…”

Section: Fcc Solver Enhancements: Regionsmentioning

confidence: 99%

“…We used benchmarks derived from verification conditions generated by DVF [9], a tool used at Intel for verifying properties of security protocols and design architectures, among other applications. Both unsatisfiable and satisfiable benchmarks were produced, the latter by manually removing necessary assumptions from verification conditions.…”

Section: Finite Model Finder Evaluationmentioning

confidence: 99%

See 1 more Smart Citation

Finite Model Finding in SMT

Computer Aided Verification

Goel

et al. 2013

Self Cite

Abstract. SMT solvers have been used successfully as reasoning engines for automated verification. Current techniques for dealing with quantified formulas in SMT are generally incomplete, forcing SMT solvers to report "unknown" when they fail to prove the unsatisfiability of a formula with quantifiers. This inability to return counter-models limits their usefulness in applications that produce quantified verification conditions. We present a novel finite model finding method that reduces these limitations in the case of quantifiers ranging over free sorts. Our method contrasts with previous approaches for finite model finding in first-order logic by not relying on the introduction of domain constants for the free sorts and by being fully integrated into the general architecture used by most SMT solvers. This integration is achieved through the addition of a novel solver for sort cardinality constraints and a module for quantifier instantiation over finite domains. Initial experiments with verification conditions generated from a deductive verification tool developed at Intel Corp. show that our approach compares quite favorably with the state of the art in SMT.

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“…The first two classes, refcount and german, represent verification conditions for systems described in [31]; benchmarks in the third are taken from [59]; the last two classes are verification problems internal to Intel. Due to proprietary restrictions on these benchmarks, we report results for an older version of cvc4 (version 1.0) that did not incorporate some of the previously mentioned enhancements.…”

Section: Efcc Solver Evaluationmentioning

confidence: 99%

Finite model finding in satisfiability modulo theories