Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Guerrieri, Andrea; Kashani-Akhavan, Sahand; Asiatici, Mikhail; Ienne, Paolo

doi:10.1109/access.2019.2931475

Cited by 2 publications

(2 citation statements)

References 11 publications

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“…OS Application Optimizations: Reconfigurable hardware components, such as accelerators and computing hardware [223], provide methods to adapt the hardware characteristics to the application requirements for improving the overall performance. A pitfall to avoid with the management of such reconfigurable hardware is to ensure that the complex algorithms that are needed to identify the suitable reconfiguration parameters for the application do not consume excessive hardware resources.…”

Section: A: Operating Systemsmentioning

confidence: 99%

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

et al. 2022

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Scalable and flexible communication networks increasingly conduct the packet processing for Network Functions (NFs) in General Purpose Computing (GPC) platforms. The input/output (I/O)-intensive and latency-sensitive packet processing is challenging for the operating systems and hypervisors running on GPC platforms. This article surveys the existing enabling technologies and research studies on operating system and hypervisor aspects that directly influence the packet processing for NFs on GPC platforms. We organize this survey according to the main categories abstraction approach, memory access, and I/O strategy. We further categorize abstraction approach technologies and research studies into the categories operation systems, hypervisors, and containers. We partition the memory access category into the two subcategories of memory allocation and memory access, while we partition the I/O strategy category into the sub-categories I/O device virtualization and I/O device access. Our survey gives a comprehensive summary of the capabilities and limitations of the existing enabling technologies and researched approaches for abstraction, memory access, and I/O for NF packet processing. We outline critical future research directions for advancing NF packet processing on GPC platforms.

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Section: A: Operating Systemsmentioning

confidence: 99%

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

et al. 2022

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“…When the mentioned resource manager indicated the use of a hardware module, its FPGA was reconfigured; otherwise, a software module was run by the CPU and performed the desired task. In other words, in those works, a good splitting algorithm of the system into the dynamic (reconfigurable) and static (non-reconfigurable) partitions is proposed [32,33].…”

Section: Related Workmentioning

confidence: 99%

Hardware Update through Digital TV Signals

et al. 2021

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This paper presents a new hardware reconfiguration approach named hardware reconfiguration through digital television (HARD), which can update FPGA hardware modules based on digital TV (DTV) signals. Such a scheme allows several synthesized hardware cores (bitstreams) signaled and broadcast through open DTV signals via data streaming to be identified, acquired, decoded, and then used for system updates. Reconfiguration data are partitioned, encapsulated into private sections, and then sent in a carrousel fashion in order to be recovered by modified receivers. Service information content, specially designed for identifying and describing the characteristics of multiplexed hardware bitstreams, was added to the transmitted signal and provided all necessary information in the traditional DTV style. The receiver framework, in turn, checked whether those characteristics corresponded to its embedded reconfigurable devices and, if a match was found, it reassembled the related bitstreams and reconfigured the respective internal circuits. Experiments performed with an implementation of the proposed methodology confirmed its feasibility and showed that remounting and reconfiguration times were satisfactory and presented no blocking aspect. Finally, HARD can be used in several designs regarding intelligent reconfigurable devices, minimize device costs in the long term, and provide better hardware reuse.

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Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Cited by 2 publications

References 11 publications

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

Hardware Update through Digital TV Signals

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