SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks

Akhlaghi, Vahideh; Yazdanbakhsh, Amir; Samadi, Kambiz; Gupta, Rajesh K.; Esmaeilzadeh, Hadi

doi:10.1109/isca.2018.00061

Cited by 135 publications

(78 citation statements)

References 25 publications

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“…Ganax [58] uses a SIMD-MIMD architecture to support DNNs and generative models. Snapea [59] employs early termination to skip computations. Instruction Sets for DNNs.…”

Section: Related Workmentioning

confidence: 99%

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network

Sharma

Park

Suda

et al. 2018

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)

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445

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Hardware acceleration of Deep Neural Networks (DNNs) aims to tame their enormous compute intensity. Fully realizing the potential of acceleration in this domain requires understanding and leveraging algorithmic properties of DNNs. This paper builds upon the algorithmic insight that bitwidth of operations in DNNs can be reduced without compromising their classification accuracy. However, to prevent loss of accuracy, the bitwidth varies significantly across DNNs and it may even be adjusted for each layer individually. Thus, a fixed-bitwidth accelerator would either offer limited benefits to accommodate the worst-case bitwidth requirements, or inevitably lead to a degradation in final accuracy. To alleviate these deficiencies, this work introduces dynamic bit-level fusion/decomposition as a new dimension in the design of DNN accelerators. We explore this dimension by designing Bit Fusion, a bit-flexible accelerator, that constitutes an array of bit-level processing elements that dynamically fuse to match the bitwidth of individual DNN layers. This flexibility in the architecture enables minimizing the computation and the communication at the finest granularity possible with no loss in accuracy. We evaluate the benefits of Bit Fusion using eight real-world feed-forward and recurrent DNNs. The proposed microarchitecture is implemented in Verilog and synthesized in 45 nm technology. Using the synthesis results and cycle accurate simulation, we compare the benefits of Bit Fusion to two state-of-the-art DNN accelerators, Eyeriss [1] and Stripes [2]. In the same area, frequency, and process technology, Bit Fusion offers 3.9× speedup and 5.1× energy savings over Eyeriss. Compared to Stripes, Bit Fusion provides 2.6× speedup and 3.9× energy reduction at 45 nm node when Bit Fusion area and frequency are set to those of Stripes. Scaling to GPU technology node of 16 nm, Bit Fusion almost matches the performance of a 250-Watt Titan Xp, which uses 8-bit vector instructions, while Bit Fusion merely consumes 895 milliwatts of power.

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“…Ganax [58] uses a SIMD-MIMD architecture to support DNNs and generative models. Snapea [59] employs early termination to skip computations. Instruction Sets for DNNs.…”

Section: Related Workmentioning

confidence: 99%

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network

Sharma

Park

Suda

et al. 2018

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)

Self Cite

445

250

View full text Add to dashboard Cite

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“…In contrast, this paper proposes an efficient model for classification of Sigfox, LoRA, IEEE 802. 15 [10]. This, however, also requires expensive and energy consuming high-end hardware to process such a vast amount of data at a high speed.…”

Section: Related Workmentioning

confidence: 99%

“…Compared to the related work, this model offers 75 to 580 times less parameters. Another way to specify the model's computational footprint is to look at the amount of multiply-accumulate (MAC) operations in the convolutional layers [15]. Moreover, a linear relationship between the MAC count and energy consumption of CNN models exists which can help to compare models suitable for embedded devices [16].…”

Section: B Model Architecturementioning

confidence: 99%

Multi-band sub-GHz technology recognition on NVIDIA’s Jetson Nano

Fontaine

Shahid

Elsas

et al. 2020

2020 IEEE 92nd Vehicular Technology Conference (VTC2020-Fall)

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Low power wide area networks support the success of long range Internet of things applications such as agriculture, security, smart cities and homes. This enormous popularity, however, breeds new challenging problems as the wireless spectrum gets saturated which increases the probability of collisions and performance degradation. To this end, smart spectrum decisions are needed and will be supported by wireless technology recognition to allow the networks to dynamically adapt to the ever changing environment where fair coexistence with other wireless technologies becomes essential. In contrast to existing research that assesses technology recognition using machine learning on powerful graphics processing units, this work aims to propose a deep learning solution using convolutional neural networks, cheap software defined radios and efficient embedded platforms such as NVIDIA's Jetson Nano. More specifically, this paper presents low complexity near-real time multi-band sub-GHz technology recognition and supports a wide variety of technologies using multiple settings. Results show accuracies around 99%, which are comparable with state of the art solutions, while the classification time on a NVIDIA Jetson Nano remains small and offers real-time execution. These results will enable smart spectrum management without the need of expensive and high power consuming hardware. Index Terms-Sub-GHz, deep learning, Software-defined radio, low-cost devices I. INTRODUCTION The Internet of things (IoT) paradigm has grown exponentially in the past decade and continues this trend into the foreseeable future. At the beginning of 2020, IoT Analytics estimated that 9.5 billion devices are connected to the Internet and forecasts a growth of 28 billion devices by 2025 [1]. This is due to the proliferation of various IoT application areas such as security, tracking, agriculture, smart metering, smart cities and smart homes. To accommodate commercial deployment of such large number of devices, recently a number of IoT technologies were developed which are called low power wide area networks (LPWANs). These technologies offer very long communication ranges allowing to connect a large number of devices using limited infrastructure cost (e.g. by installing a small number of gateways). Example technologies include Sigfox, LoRA, IEEE 802.11ah, IEEE 802.11g, Dash7, Weightless, etc. These technologies operate in unlicensed sub-GHz band, typically 868 MHz in Europe and 915 MHz in North America. These radio frequencies offer good object penetration performance and can be used for a long range of communication, i.e., up to 15 km (for LoRa) [2]. However, due to

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“…Output sparsity In addition to exploiting input neuron sparsity, x t and h t , prior work exploits sparsity in output neurons [14], [64]. This requires predicting output neurons that will be masked by ReLU.…”

Section: A Design Space Explorationmentioning

confidence: 99%

MASR: A Modular Accelerator for Sparse RNNs

Gupta

Reagen

Pentecost

et al. 2019

2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)

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Recurrent neural networks (RNNs) are becoming the de facto solution for speech recognition. RNNs exploit longterm temporal relationships in data by applying repeated, learned transformations. Unlike fully-connected (FC) layers with single vector matrix operations, RNN layers consist of hundreds of such operations chained over time. This poses challenges unique to RNNs that are not found in convolutional neural networks (CNNs) or FC models, namely large dynamic activation. In this paper we present MASR, a principled and modular architecture that accelerates bidirectional RNNs for on-chip ASR. MASR is designed to exploit sparsity in both dynamic activations and static weights. The architecture is enhanced by a series of dynamic activation optimizations that enable compact storage, ensure no energy is wasted computing null operations, and maintain high MAC utilization for highly parallel accelerator designs. In comparison to current state-of-the-art sparse neural network accelerators (e.g., EIE), MASR provides 2× area 3× energy, and 1.6× performance benefits. The modular nature of MASR enables designs that efficiently scale from resourceconstrained low-power IoT applications to large-scale, highly parallel datacenter deployments.

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SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks

Cited by 135 publications

References 25 publications

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network

Multi-band sub-GHz technology recognition on NVIDIA’s Jetson Nano

MASR: A Modular Accelerator for Sparse RNNs

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