SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

Rios

Peón-Quirós

et al. 2020

Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a "simple" replacement of eFlash in micro-controller and introducing RRAM inside the memory hierarchy is not a straightforward move. Indeed, integrating a RRAM technology inside the cache hierarchy requires higher endurance requirement than for eFlash replacement, and thus necessitates relaxed programming conditions. By doing so, the reliability bottleneck is moved from programming to the read operations (i.e., read margin is reduced and the risk of read failure is increased). Based on this observation, in this work, we propose to explore how Edge-level applications running on a RRAM-based Edge device could fail because of Bias Temperature Instability (BTI). BTI causes threshold voltage (Vt) degradation on the transistors along the memory WordLines (WL), leading to a reduction of the read margin along regularly used WLs. We thereby propose a 3-steps methodology consisting in (i) characterizing the RRAM bitcell and identifying beyond which Vt shift the read operation is going to fail. (ii) characterizing applications and extracting the memory traces. And (iii) running a long term BTI simulation to extract the actual Vt shift of the bitcells sharing the same array WordLine. Based on this, we show that for a 1T1R bitcell featuring a 250% High/Low Resistance State (HRS/LRS) ratio, read failures tend to happen after less than a month in the case of a constantly running convolution kernel. These simulations highlight the fact that transistor-level reliability can be critical for embedded RRAM and that specific workload aware simulation frameworks are required to assess their effects.

Section: A Resistive Memory Architecturesmentioning

confidence: 99%

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

Rios

Peón-Quirós

et al. 2020

“…This architecture, named crosspoint (or crossbar) [7], suffers of new constraints such as the sneakpath currents and programming current control. As the selection transistor has been suppressed, the leakage current through unselected bitcells (sneakpath) is less controlled and leads to lower read margins [13] and distorted programming current Iprog [10].…”

Section: B High Density Rram Architecturesmentioning

confidence: 99%

RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations

2018 Conference on Design of Circuits and Integrated Systems (DCIS)

Giraud

Noël

et al. 2018

Self Cite

As more and more high density memories are required to satisfy the Internet of Things ecosystem, academics and industrials are looking for an intermediate solution to fill the gap between DRAM and Flash NAND in the memory hierarchy. The emergence of Resistive Switching Technologies (RRAM) proposes a potential solution to this demand for fast, low cost, high density and non-volatile memory. However, nowadays transistorless RRAM-based architectures, such as Crosspoint, suffers of several issues such as sneakpath, IRdrop and periphery overhead. In this work, we propose to explore the positioning of RRAM crosspoint memories regarding DRAM and NAND in terms of density and write throughput. We present several design guidelines then show that for the optimal RRAM crosspoint architecture (2-layers with common bitline), massively multiple bank write is the solution to optimize density and write throughput to around 20-100Gbit/cm2 and 200-500MB/s respectively for 32 to 64 parallel access.

“…To overcome these limitations, a BEoL selector has to be integrated in the RRAM stack. In 1S1R configuration, the SP effect is mitigated and can be efficiently compensated [25] [27] still allowing a dense 4 2 bitcell area only limited by metal pitch. However, this BEoL selector causes an increase of the programming voltages of a factor 2 at least increasing the programming voltage of the bitcells from 1 to 1.5V [6] [9] up to more than 2.5V [14] [28].…”

Section: Background a 1 Selector -1 Resistance Bitcell Modelmentioning

confidence: 99%

Architecture, design and technology guidelines for crosspoint memories

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

Royer

Giraud

et al. 2017

Self Cite

While standalone Flash memories (NAND) are facing their physical limitations, the emergence of resistive switching memories (RRAM) is seen as a solution for high density, low cost and low energy NAND replacement candidate. However, it has been shown that deeply scaled, high density RRAM architectures, such as crosspoint, suffer of voltage drop effects (IR drop) in metal lines, periphery overhead and metal line charging time due to injected current during programming operations and sneaking currents through unselected bitcells. In this work, we first propose several innovative models for IRdrop, periphery overhead and array-line charging time accounting for in-array multiple bit-write operation. Then, we introduce a new methodology for crosspoint memory design to determine IRdrop, periphery overhead and timing associated with the optimal characteristics of 1 selector-1 resistance (1S1R) device. We apply the proposed methodology to various half metal pitch memory technology nodes (from 50nm to 15nm) and to several written word sizes (from 1 to 32 bits). We show that for 1 bit programmed per array, the RRAM programming current has to be lower than 30µA and the selector leakage current lower than 10nA and that limitations increase as soon as multiple bits are written simultaneously in the same array. This, suggests massively parallel multi-bank write of a small number of bits per array, as the best solution for the RRAM memories to be competitive with NAND memories