SnSe/MoS₂ van der Waals Heterostructure Junction Field‐Effect Transistors with Nearly Ideal Subthreshold Slope

Abstract

The minimization of the subthreshold swing (SS) in transistors is essential for low‐voltage operation and lower power consumption, both critical for mobile devices and internet of things (IoT) devices. The conventional metal‐oxide‐semiconductor field‐effect transistor requires sophisticated dielectric engineering to achieve nearly ideal SS (60 mV dec−1 at room temperature). However, another type of transistor, the junction field‐effect transistor (JFET) is free of dielectric layer and can reach the theoretical SS limit without complicated dielectric engineering. The construction of a 2D SnSe/MoS2 van der Waals (vdW) heterostructure‐based JFET with nearly ideal SS is reported. It is shown that the SnSe/MoS2 vdW heterostructure exhibits excellent p–n diode rectifying characteristics with low saturate current. Using the SnSe as the gate and MoS2 as the channel, the SnSe/MoS2 vdW heterostructure exhibit well‐behavioured n‐channel JFET characteristics with a small pinch‐off voltage VP of −0.25 V, nearly ideal subthreshold swing SS of 60.3 mV dec−1 and high ON/OFF ratio over 106, demonstrating excellent electronic performance especially in the subthreshold regime.

Transferred metal gate to 2D semiconductors for sub-1 V operation and near ideal subthreshold slope

“…To eliminate the use of high-k dielectrics in FETs, an alternative approach is to adopt junction capacitance in the gate terminals of FETs, e.g., the pn junction in junction FETs (JFETs) and Schottky junction in metal-semiconductor FETs (MESFETs), which usually have much larger capacitance than dielectric capacitance and show efficient electrostatic gate control (3,14). The surface potential changes in JFETs and MESFETs are equal to the gate voltage (14)(15)(16). Compared with JFET, the MESFET has a simple structure and is relatively easy to fabricate.…”

MoS2 Homojunctions Transistors Enabled by Dimension Tailoring Strategy

“…In order to further study the temperature effect on electrical characteristics of MoS 2 MESFETs, the I DS -V GS curves are obtained at varied temperatures from 77 to 300 K. As shown in Figure 2d, I DS decreases with increasing temperature and tend to saturate under a large V GS , which can be mainly ascribed to the enhanced scattering with temperature or the release of www.advelectronicmat.de trapped electrons at the interface. [28] In Figure S8, Supporting Information, the V TH of MoS 2 MESFETs shifts to negative values and I DS decreases as temperature increases, finally showing a low V TH of −1.08 V at 77 K. Figure 2e shows typical transfer characteristics of MoS 2 MESFETs with various V DS from 0.1 to 5.0 V at 77 K, indicating improved on-state current, and off-state current maintains a relative low level. In Figure 2f, the maximum output current of 140 µA•µm −1 can be achieved at V GS = 4.0 V at 77 K.…”

Ambipolar Channel p‐TMD/n‐Ga2O3 Junction Field Effect Transistors and High Speed Photo‐sensing in TMD Channel

“…The linear mobility for electron carrier transport appears to be ≈4 cm 2 V −1 s −1 which is quite lower than that of p‐channel JFET but comparable to those of other reports. [ 2,11,35,36 ] The threshold voltage (V th ) in n‐channel JFET appears larger than −4 V (V th for p‐channel ≈−2 V) when V th is defined as the gate voltage at 1 nA of I DS . We ascribe such large V th to the channel thickness of n‐Ga 2 O 3 which is as large as ≈300 nm.…”

“…Until recent years, 2D PN junctions using transition metal dichalcogenide (TMD) semiconductors have been extensively reported, showing novel properties in respect of junction interface. [ 1–8 ] They are based on van der Waals heterojunctions in many cases. However, fabricating such heterojunctions using two different 2D TMD flakes should not be easy at all because each different Ohmic contact for p‐ and n‐type layer is difficult to obtain in practicality.…”