SoC Instrumentations: Pre-Silicon Preparation for Post-Silicon Readiness

Ray, Sandip

doi:10.1007/978-3-319-98116-1_2

Cited by 1 publication

(1 citation statement)

References 11 publications

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“…Contemporary works in this field, particularly post-silicon debug, can be found in [12][13][14][15]. Indeed, post-silicon debug readiness needs to be prepared early in the design [16][17][18]. A number of authors extend the idea to other areas such as machine learning [19,20].…”

Section: Introductionmentioning

confidence: 99%

On-chip debugging for microprocessor design

2020

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This article proposes a closer-to-metal approach of RTL inspection in microprocessor design for use in education, engineering, and research. Signals of interest are tapped throughout the microprocessor hierarchical design and are then output to the top-level entity and finally displayed to a VGA monitor. Input clock signal can be fed as slow as one wish to trace or debug the microprocessor being designed. An FPGA development board, along with its accompanying software package, is used as the design and test platform. The use of VHDL commands 'type' and 'record' in the hierarchy provides key ingredients in the overall design, since this allows simple, clean, and tractable code. The method is tested on MIPS single-cycle microprocessor blueprint. The result shows that the technique produces more consistent display of the true contents of registers, ALU input/output signals, and other wires-compared to the standard, widely-used simulation method. This approach is expected to increase confidence in students and designers since the reported signals' values are the true values. Its use is not limited to the development of microprocessors; every FPGAbased digital design can benefit from it. This is an open access article under the CC BY-SA license.

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