SoC Research and Development Platform for Distributed Embedded Systems

Krzywicki, Kazimierz; Barkalov, Alexander; Andrzejewski, G.; Titarenko, Larysa; Kołopieńczyk, M.

doi:10.15199/48.2016.10.59

Cited by 7 publications

(7 citation statements)

References 6 publications

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“…, p G } and implements the SBF (8). The Blockδ generates input memory functions (9) and additional variables z r ∈ Z used for encoding of collections of outputs Y q ⊆ Y(q ∈ {1, . .…”

Section: State-of-the-artmentioning

confidence: 99%

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Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

et al. 2020

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Contemporary digital systems include many varying sequential blocks. In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. In many cases, the performance is the most important characteristic of an FSM circuit. In the article, we propose a method which allows increasing the operating frequency of multi-level look-up table (LUT)-based Mealy FSMs. The main idea of the proposed approach is to use together two methods of structural decomposition. They are: (1) the known method of transformation of codes of collections of outputs into FSM state codes and (2) a new method of extension of state codes. The proposed approach allows producing FPGA-based FSMs having three levels of logic combined through the system of regular interconnections. Each function for every level of logic was implemented using a single LUT. An example of the synthesis of Mealy FSM with the proposed architecture is shown. The effectiveness of the proposed method was confirmed by the results of experimental studies based on standard benchmark FSMs. The research results show that FSM circuits based on the proposed approach have a higher operating frequency than can be obtained using other investigated methods. The maximum operating frequency is improved by an average of 3.18 to 12.57 percent. These improvements are accompanied by a small growth of LUT count.

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“…, p G } and implements the SBF (8). The Blockδ generates input memory functions (9) and additional variables z r ∈ Z used for encoding of collections of outputs Y q ⊆ Y(q ∈ {1, . .…”

Section: State-of-the-artmentioning

confidence: 99%

“…However, very often the performance is a critical factor for a digital system. For example, it is true for real-time embedded systems [8,9]. If a multi-level circuit does not provide the required performance, then the number of levels should be decreased.…”

Section: Introductionmentioning

confidence: 99%

Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

et al. 2020

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“…The majority of modern FPGAs are organized using so called "island-style" architecture [16,28,30]. They include different configurable logic blocks (CLBs) and a matrix of programmable interconnections [10][11][12].…”

Section: Specifics Of Fpgas and Mealy Fsmsmentioning

confidence: 99%

Reducing LUT Count for FPGA-Based Mealy FSMs

2020

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Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method optimizing LUT counts of LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the replacement of FSM inputs and encoding of the collections of outputs. The proposed method results in three-level logic circuits of Mealy FSMs. These circuits have regular systems of interconnections. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). This gain is accompanied by a small loss of FSM performance.

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“…To specify the behaviour of a sequential block, it is necessary to use some formal model. In many cases, the behaviour of sequential blocks is specified by Mealy finite state machines (FSMs) [4][5][6][7]. Three main characteristics determine the quality of an FSM circuit: the chip area occupied by the circuit, performance (either minimum propagation time or maximum operating frequency), and the consumption of power.…”

Section: Introductionmentioning

confidence: 99%

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

et al. 2021

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Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.

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SoC Research and Development Platform for Distributed Embedded Systems

Cited by 7 publications

References 6 publications

Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

Reducing LUT Count for FPGA-Based Mealy FSMs

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

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