SoC/SoPC Development using MDD and MARTE Profile

Aulagnier, Denis; Koudri, Ali; Lecomte, Stéphane; Soulard, Philippe; Champeau, Joël; Vidal, Jorgiano; Perrouin, Gilles; Leray, Pierre

doi:10.1002/9781118558096.ch8

Cited by 4 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…As a complete environment for embedded and RTS design, the MOPCOM methodology [3,27,49] is based on three design levels. Regarding the first level, it presents abstract models for system behavior and requirements.…”

Section: Mde and Rts Designmentioning

confidence: 99%

Transformation process of RTS scheduling analysis requirements from UML/MARTE to dynamic priority time Petri Nets

Mahfoudhi

Karamti

2015

J Supercomput

View full text Add to dashboard Cite

The real-time system (RTS) design is a major challenge due to the complexity of the considered application and the appearance of multiprocessor architectures. Most of the research in this area is interested in high abstraction level methods to decrease the design convolution. In particular, the Unified Modeling Language (UML) profiles and the Model Driven Engineering (MDE) aim at being an adequate solution to support the whole life cycle of RTS design with its real-time constraints and performance issues. Based on MDE and the Modeling and Analysis of Real-Time and Embedded systems (MARTE) profile, the present manuscript proposes an interactive partitioning scheduling of RTS running on multiprocessor architecture. A special attention is paid to the scheduling analysis step to accelerate the exploration of HW/SW space solution. Starting from a candidate solution modeled with UML activity and annotated with MARTE stereotypes, a mapping process to dynamic priority time Petri Nets (dPTPN) was defined. The considered dPTPN is able to prove the schedulability or provide a counterexample to determine the partitions causes of temporal fault. This counterexample presents a useful feedback to the HW/SW space solution explorer in the aim to exclude all solution containing the described partitions.

show abstract

Section: Mde and Rts Designmentioning

confidence: 99%

Transformation process of RTS scheduling analysis requirements from UML/MARTE to dynamic priority time Petri Nets

Mahfoudhi

Karamti

2015

J Supercomput

View full text Add to dashboard Cite

show abstract

“…After the wide and successful application of UML in the area of software engineering, there is a growing interest in the use of UML at the high level of abstraction for modeling hardware designs. To this aim, researchers have created UML profiles such as UML-SystemC [2], UML-SoC [18], MARTE [8], or SysML [3] that extend UML with the appropriate constructs to hierarchically describe complex hardware designs and analyze their properties. Thereafter, they have created approaches to generate a system level implementation through imperative intermediate HDL code such as VHDL [3,5], Verilog [5,7] or SystemC [1,2,5,6], to bridging the gap between UML high level description and the micro-architecture level description.…”

Section: Introductionmentioning

confidence: 99%

A SysML and CLEAN-based methodology for digital circuits design

Lakhdara¹,

Merniz²

2016

IJHPSA

View full text Add to dashboard Cite

Due to the ever complexity of digital systems, there is a noticeable need for more abstract and structural mechanisms as well as design methodologies that systematically and formally derive low level concrete designs from high level abstract ones. To this aim, we present a methodological design approach that automatically generates a functional HDL code from SysML diagrams modeling hardware designs. The generated HDL code is both reliable and executable. While the first feature remains crucial for low level design refinements, the second one enables evaluating design performances at early stages. A case study involving the functional implementation of an ALU (Arithmetic Logic Unit) through Clean code generated from high level SysML diagrams is given, to practically show the potential features of the proposed approach.

show abstract

“…No MDA, o processo de modelagem trabalha com níveis respectivos às necessidades particulares (Aulagnier et al, 2009;Koudri et al, 2009): A figura 8 descreve o processo de alocação de modelos em MDA. São entrados dois esquemas: o funcional e uma modelagem AML.…”

Section: Visão De Fusãounclassified

“…Figura 8: Processo de alocação de modelos AML (Abstract Modeling Level) e funcional. Tal processo utiliza-se de combinação de dois modelos, uma análise estratégica da comunicação e concorrência, e uma transformação num modelo já alocado (Aulagnier et al, 2009). (Miller & Mukerji, 2003).…”

Section: Visão De Fusãounclassified

Um gerador de sistemas embarcados a partir de modelo independente de plataforma baseado no perfil MARTE

Filho¹,

Medeiros²

View full text Add to dashboard Cite

À CAPES pelo apoio financeiro. À FAPESP pelo apoio de viagens. À Pós-graduação do ICMC-USP pelo apoio intelectual. À Association for Computing Machinery, pelas menções honoráveis como coach do ICPC. Ao Prof. Dr. Vanderlei Bonato, meu orientador, pelo apoio intelectual e dedicação. À Microsoft, pela liderança nas células acadêmicas UNICAP.NET e WINFX-GT. Ao Prof. Dr. Francisco Madeiro Bernardino Junior, pelo 1o lugar CCET/PIBIC/CNPq Aos meus pais, Profa. Lauriane e Sr. Roberto. A todos meus professores, parentes e amigos. A Deus, por tudo.

show abstract

SoC/SoPC Development using MDD and MARTE Profile

Cited by 4 publications

References 5 publications

Transformation process of RTS scheduling analysis requirements from UML/MARTE to dynamic priority time Petri Nets

Transformation process of RTS scheduling analysis requirements from UML/MARTE to dynamic priority time Petri Nets

A SysML and CLEAN-based methodology for digital circuits design

Um gerador de sistemas embarcados a partir de modelo independente de plataforma baseado no perfil MARTE

Contact Info

Product

Resources

About