SoCCom: Automated Synthesis of System-on-Chip Architectures

Nath, Atul Prasad Deb; Raj, Kshitij; Bhunia, Swarup; Ray, Sandip

doi:10.1109/tvlsi.2022.3141326

Cited by 6 publications

(1 citation statement)

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“…The received data from the source system i.e. the device which is generating electrocardiogram (ECG) signals are stored in FIFO if other flits are awaiting traversal or if the arbiter does not provide grant access to the output port [25]. The FIFO control block (FCB) will take care of the FIFO pointer arithmetic and control the corresponding input port's signal flow.…”

Section: Proposed Low Power Router Design For Label Switching-noc'smentioning

confidence: 99%

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Patil,

Sandi

2024

IJRES

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The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

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Section: Proposed Low Power Router Design For Label Switching-noc'smentioning

confidence: 99%