SoCIN: a parametric and scalable network-on-chip

Zeferino, Cesar Albenes; Susin, Altamiro

doi:10.1109/sbcci.2003.1232824

Cited by 114 publications

(86 citation statements)

References 8 publications

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“…Layouts are presented in [20], [21], a test chip is shown in [22], and an FPGA target is provided for [23], [24]. Synthesis and layout results for the ×pipes library of component blocks that we will leverage upon are detailed in [25], [26].…”

Section: B Network-on-chipmentioning

confidence: 99%

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Loi

Angiolini

Benini

2007

Proceedings of the Second International Conference on Nano-Networks

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Abstract-Three-dimensional (3D) manufacturing technologies are viewed as promising solutions to the bandwidth bottlenecks in VLSI communication. At the architectural level, Networkson-chip (NoCs) have been proposed to address the complexity of interconnecting an ever-growing number of cores, memories and peripherals. NoCs are a promising choice for implementing scalable 3D interconnect architectures. However, the development of 3D NoCs is still at an early development stage. In this paper, we present a semi-automated design flow for 3D NoCs. Starting from an accurate physical and geometric model of ThroughSilicon Vias (TSVs), we extract a circuit-level model for vertical interconnections, and we use it to evaluate the design implications of extending switch architectures with ports in the vertical direction. In addition, we present a design flow allowing for post-layout simulation of NoCs with links in all three physical dimensions.

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Section: B Network-on-chipmentioning

confidence: 99%

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Loi

Angiolini

Benini

2007

Proceedings of the Second International Conference on Nano-Networks

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“…In this paper, we base our analysis on a packet-switching network model, so-called SoCIN, introduced in [27]. It is implemented in a two-dimensional mesh topology.…”

Section: Background: Nocmentioning

confidence: 99%

Constraint-Driven Test Scheduling for NoC-Based Systems

Cota¹,

Liu

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-On-chip integrated network, the so-called networkon-chip (NoC), is becoming a promising communication paradigm for the next-generation embedded core-based system chips. The reuse of the on-chip network as test access mechanism has been recently proposed to handle the growing complexity of testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various constraints. Therefore, efficient test-scheduling methods are required to deliver feasible test time while meeting all the constraints. In this paper, the authors propose a comprehensive approach to test scheduling in NoC-based systems. The proposed scheduling algorithm is based on the use of dedicated routing path that is suitable for nonpreemptive test. The algorithm is improved by incorporating both preemptive and nonpreemptive tests. In addition, BIST, precedence, and power constraints were taken into consideration. Experimental results for the ITC'02 system-on-chip benchmarks show that the nonpreemptive scheduling based on dedicated path can efficiently reduce test application time compared to previous work, and the improved method provides a practical solution to the real-world NoC-based-system testing with both preemptive and nonpreemptive cores. It is also shown that various constraints can be incorporated to deliver a comprehensive test solution.Index Terms-Network-on-chip (NoC), system-on-chip (SoC) testing, test access mechanism (TAM), test scheduling.

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“…Different NoCs solutions are used in MPSoC platforms and commercialized by many companies such as SonicsGN [5] developed by Sonics, FlexNoC [6] by Arteris, AEthereal NoC [7] by Philips Research Laboratories and Teraflops Research Chip (also called Polaris) [8,9] by Intel Corporation's TeraScale Computing Research Program. Other NoC-based multicore system architectures are developed by teams from universities and research institutions such as SoCIN [10], OCCN [11], FAUST [12] and Ninesilica [13].…”

Section: Introductionmentioning

confidence: 99%

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Salem¹,

Salah²,

Bennour³

et al. 2017

ijacsa

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Abstract-Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some perceived challenges. Overcoming those challenges with the right prototyping solutions is easy and cost-effective leading to much faster time-to-market. In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC. A case study of two-dimensional mesh NoC-based MPSoC architecture is presented with a validation environment. The synthesis and implementation results of the NoC-based MPSoC on a Virtex 5 ML 507 enable a reasonable frequency (151.5 MHz) and a resource usage rate equals to 58% (6,586 out of 11,200 slices used).

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SoCIN: a parametric and scalable network-on-chip

Cited by 114 publications

References 8 publications

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Constraint-Driven Test Scheduling for NoC-Based Systems

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

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