Soft/write-error-resilient CMOS/magnetic tunnel junction nonvolatile flip-flop based on majority-decision shared writing

Abstract

A soft/write-error-resilient nonvolatile flip-flop (NVFF) using three-terminal magnetic tunnel junctions (MTJs) is presented. The proposed NVFF exploits a redundant structure with a majority bit implicitly stored, which is tolerant to soft errors including both single-event transients (SETs) and single-event upsets (SEUs). For write-error resilience, all the bits of the redundant MTJs are written using the majority bit with a shared writecurrent path, exhibiting 1-bit soft-error correction and 1-bit write-error masking. In addition, the shared writing scheme reduces the number of writecurrent paths to one-third of that with a redundant NVFF with 1-bit soft/write-error masking. Using 65 nm CMOS/MTJ technologies, the proposed NVFF achieves a few orders-of-magnitude reduction in the failure in time (FIT), a 31% reduction in the transistor count, and a 65% reduction in the write energy in comparison with the redundant NVFF.

Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

“…10. The nonvolatile processors 20,21,26,27) include nonvolatile flip-flops (NVFFs) [28][29][30] to back up data in the processor. In addition, the nonvolatile memory, such as MRAMs and ReRAMs, [15][16][17] is used to back up data.…”