Software-based self-test generation for microprocessors with high-level decision diagrams

Abstract

This paper presents a novel approach to automated behavioural level test program generation for microprocessors using the model of high-level decision diagrams (HLDD) for representing instruction sets. The methodology of using HLDDs for modelling of microprocessors, and a new HLDD-based fault model are developed. The procedures for automated test program generation are presented using a formal model of HLDDs. The feasibility and efficiency of the new methodology are demonstrated by carrying out experimental research on test generation for a 8-bit microprocessor. The results are promising, showing the advantages of the new method and demonstrating better quality of tests compared to previous results. A. Jasnetski et al.: Self-test generation for microprocessors49 test program generation method, which must comply with the high-quality fault coverage standards imposed by the industry.In general, the development of the SBST program consists of four steps: 1) creation and optimization of test pattern delivery templates in assembly language, 2) module-level instruction imposed (functional) constraint extraction, 3) test generation process for each module of the processor under test, 4) translation of test patterns to self-test programs.The last step is basically a process of joining the test pattern with the test pattern delivery template. Initial focus of the research was on the fault coverage of the tests. The fault coverage of the SBST test is primarily affected by the test patterns. One of the ways to obtain test patterns is to run ATPG. In [5] it was shown that the processor can be divided into modules under tests (MUTs) to ease the task of ATPG. The other way is to use random test patterns for MUTs [6]. Although the gate level fault coverage for MUT is acceptable in deterministic and random test pattern generation, some of the generated patterns are typically functionally infeasible when considering the processor as a whole. The latter requires a manual effort to collect the constraints that guide ATPG at gate level. Obviously, considering todays complexity of the gate level processor implementation it is not feasible to have manual operations at the gate level.An automatic constraint extraction, based on the gate level simulation of generated tests to check their functional feasibility, was proposed in [7]. But the efficiency of the method on the industrial processors was known to be low. In [8] it is suggested to shift test pattern generation from the gate level to the RT level. This is achieved by the reuse of the verification test patterns. The drawback of this method is that high fault coverage for structural faults cannot be guaranteed by verification test patterns.Considering the drawbacks of the previously mentioned methods we followed the idea to benefit from the test generation at gate level and to collect functional constraints at RT level description of the processor. One of the papers [9] shows the possibility to use the bounded model checker (BMC) to map the pregenerated test patterns into delivery ...