Software energy optimization through fine-grained function-level voltage and frequency scaling

Brandolese, Carlo; Fornaciari, William

doi:10.1145/2380445.2380528

Cited by 2 publications

(1 citation statement)

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“…The methodology has been applied to several benchmarks and the estimates compared with the most accurate available figures, i. e. those obtained with a targetspecific, power-enabled instruction-set simulator [69]. The absolute estimation errors obtained on a set of several benchmarks ranges from less than 2% up to to 13%, with an average of 6%.…”

Section: Llvm Code)mentioning

confidence: 99%

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

Grüttner

Hartmann

Hylla

et al. 2013

Microprocessors and Microsystems

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The consideration of an embedded device’s power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of today’s heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project

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Section: Llvm Code)mentioning

confidence: 99%