Software synthesis and code generation for signal processing systems

Bhartacharyya, S.S.; Leupers, Rainer; Marwedel, Peter

doi:10.1109/82.868454

Cited by 61 publications

(51 citation statements)

References 81 publications

(103 reference statements)

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“…Similarly, a compiler for a general-purpose HLL (such as C) typically does not have the global information about application structure that our allocator has. The techniques we develop in this paper are thus complementary to the work that is being done on developing better HLL compilers for DSPs (e.g., see [8][9][10][11][12]). In particular, the techniques we develop operate on the graphs at a high enough level that particular architectural features of the target processor are largely irrelevant.…”

Section: Introductionmentioning

confidence: 99%

“…1, each edge is annotated with the number of tokens produced (consumed) by its source (sink) actor. Although the synchronous dataflow assumption imposes significant restrictions on program structure, the model is broad enough to cover a broad class of important signal processing applications and is the basis for several commercial design tools [9]. We review existing relevant work and contrast our work in Section 3.…”

Section: Problem Statement and Organization Of The Papermentioning

confidence: 99%

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The CBP Parameter: A Module Characterization Approach for DSP Software Optimization

Bhattacharyya

Murthy

2004

The Journal of VLSI Signal Processing-Systems for Signal, Image

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Abstract. Memory consumption is an important metric for DSP software implementation. In this paper, we develop a module characterization technique that promotes more economical use of memory resources at the system level. Our work is developed in the context of software synthesis from signal/video/image processing applications expressed as synchronous dataflow (SDF) graphs. SDF is a restricted form of dataflow where each computational module (actor) consumes and produces a fixed number of data values (tokens) on each execution. Usually, no assumption is made about when during the execution of an actor, the tokens are actually consumed and produced; the firing of an actor is treated as an atomic event for most purposes. However, we show in this paper that it is possible to concisely and precisely capture key properties pertaining to the relative times at which tokens are produced and consumed by an actor. We show this by introducing the consumed-before-produced (CBP) parameter, which provides a general method for characterizing the token transfer of an SDF actor. Good bounds on the CBP parameter can aid an SDF compiler in performing more aggressive optimizations for reducing buffer sizes on the edges between actors. We formally define the CBP parameter; derive some useful properties of this parameter; illustrate how the value of the parameter is derived by examining in detail the multirate FIR filter, which is a fundamental actor in multirate signal processing applications; and examine CBP parameterizations for several other practical SDF actors.

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Section: Introductionmentioning

confidence: 99%

Section: Problem Statement and Organization Of The Papermentioning

confidence: 99%

The CBP Parameter: A Module Characterization Approach for DSP Software Optimization

Bhattacharyya

Murthy

2004

The Journal of VLSI Signal Processing-Systems for Signal, Image

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“…Looped schedules are useful for software code generation from a dataflow graph as every actor appearance in a looped schedule can be replaced by a function call (or inline code), and parenthesized terms can be replaced by software loops to generate complete executable code for an application [1]. Looped schedules are also useful in generating test benches with which different hardware alternatives can be functionally validated.…”

Section: Would Be (Sabc)(rde(8fg))(q 2 Zh)mentioning

confidence: 99%

“…This opens up design space exploration opportunities for meeting different user constraints, and achieving different implementation trade-offs. However, streamlining the use of dataflow technology is challenging because it requires careful mapping of application characteristics into the graphical and actor-based modeling abstractions of dataflow, and because the associated optimization issues, while exposed more effectively for signal processing applications compared to other modeling abstractions, are usually NP-complete to solve exactly [1].…”

Section: Fpga Technologymentioning

confidence: 99%

“…The granularity of dataflow representations can range from fine-grained, where actors represent individual operations such as addition or multiplication, to coarse-grained, where actors typically represent sub-graphs or code segments on the order of 10-100 lines. Dataflow is widely used in the design of signal processing applications because it is an intuitive mode for algorithm designers to work with, and it also exposes highlevel application structure that is useful for analysis, verification, and optimization of implementations [1].…”

Section: Dataflow Modelingmentioning

confidence: 99%

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Model-based mapping of reconfigurable image registration on FPGA platforms

Sen

Hemaraj

Plishker

et al. 2008

J Real-Time Image Proc

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Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images.

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Consistency Analysis of Reconfigurable Dataflow Specifications

Bhattacharya

Bhattacharyya

2002

Embedded Processor Design Challenges

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Abstract. Parameterized dataflow is a meta-modeling approach for incorporating dynamic reconfiguration capabilities into broad classes of dataflow-based design frameworks for digital signal processing (DSP). Through a novel formalization of dataflow parameterization, and a disciplined approach to specifying parameter reconfiguration, the parameterized dataflow framework provides for automated synthesis of robust and efficient embedded software. Central to these synthesis objectives is the formulation and analysis of consistency in parameterized dataflow specifications. Consistency analysis of reconfigurable specifications is particularly challenging due to their inherently dynamic behavior. This paper presents a novel framework, based on a concept of local synchrony, for managing consistency when synthesizing implementations from dynamicallyreconfigurable, parameterized dataflow graphs. Motivation and related workDataflow is an established computational model for simulation and synthesis of software for digital signal processing (DSP) applications. The modern trend toward highly dynamic and reconfigurable DSP system behavior, however, poses an important challenge for dataflow-based DSP modeling techniques, which have traditionally been well-suited primarily for applications with significantly static, high-level structure. Parameterized dataflow [1] is a promising new meta-modeling approach that addresses this challenge by systematically incorporating dynamic reconfiguration capabilities into broad classes of dataflow-based design frameworks for digital signal processing (DSP).Through a novel formalization of dataflow parameterization, and a disciplined approach to specifying parameter reconfiguration, the parameterized dataflow framework provides for automated synthesis of robust and efficient embedded software.

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Software synthesis and code generation for signal processing systems

Cited by 61 publications

References 81 publications

The CBP Parameter: A Module Characterization Approach for DSP Software Optimization

The CBP Parameter: A Module Characterization Approach for DSP Software Optimization

Model-based mapping of reconfigurable image registration on FPGA platforms

Consistency Analysis of Reconfigurable Dataflow Specifications

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