Software Transactional Memory on Relaxed Memory Models

Guerraoui, Rachid; Henzinger, Thomas A.; Singh, Vasu

doi:10.1007/978-3-642-02658-4_26

Cited by 23 publications

(13 citation statements)

References 20 publications

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“…Various formalisms for memory models have been proposed in the literature [3,4,5,12,23,24]. Most of these formalisms are tailored to capture the intricacies of specific memory models.…”

Section: Discussionmentioning

confidence: 99%

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Transactions in the jungle

Guerraoui

Henzinger

Kapalka

et al. 2010

Proceedings of the Twenty-Second Annual ACM Symposium on Parallelism in Algorithms and Architectures

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Transactional memory (TM) has shown potential to simplify the task of writing concurrent programs. Inspired by classical work on databases, formal definitions of the semantics of TM executions have been proposed. Many of these definitions assumed that accesses to shared data are solely performed through transactions. In practice, due to legacy code and concurrency libraries, transactions in a TM have to share data with non-transactional operations. The semantics of such interaction, while widely discussed by practitioners, lacks a clear formal specification. Those interactions can vary, sometimes in subtle ways, between TM implementations and underlying memory models.We propose a correctness condition for TMs, parametrized opacity, to formally capture the now folklore notion of strong atomicity by stipulating the two following intuitive requirements: first, every transaction appears as if it is executed instantaneously with respect to other transactions and non-transactional operations, and second, non-transactional operations conform to the given underlying memory model. We investigate the inherent cost of implementing parametrized opacity. We first prove that parametrized opacity requires either instrumenting non-transactional operations (for most memory models) or writing to memory by transactions using potentially expensive read-modify-write instructions (such as compare-and-swap). Then, we show that for a class of practical relaxed memory models, parametrized opacity can indeed be implemented with constant-time instrumentation of non-transactional writes and no instrumentation of non-transactional reads. We show that, in practice, parametrizing the notion of correctness allows developing more efficient TM implementations.

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“…Various formalisms for memory models have been proposed in the literature [3,4,5,12,23,24]. Most of these formalisms are tailored to capture the intricacies of specific memory models.…”

Section: Discussionmentioning

confidence: 99%

“…Most of the TM implementations [8,14] satisfy opacity. The formal definition of opacity has allowed for a clear understanding of transactions [13] and also for development of model checking techniques for TM algorithms [10,11,12].…”

Section: Introductionmentioning

confidence: 99%

Transactions in the jungle

Guerraoui

Henzinger

Kapalka

et al. 2010

Proceedings of the Twenty-Second Annual ACM Symposium on Parallelism in Algorithms and Architectures

Self Cite

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“…Language level memory models have been developed for Java [29] and C++ [3]. Various formalisms for memory models have been proposed in the literature [4,7,21,35,36]. Most of these formalisms provide an axiomatic definition of memory models.…”

Section: Formalisms For Relaxed Memory Modelsmentioning

confidence: 99%

Verification of STM on relaxed memory models

Guerraoui

Henzinger

Singh

2011

Form Methods Syst Des

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Software transactional memories (STM) are described in the literature with assumptions of sequentially consistent program execution and atomicity of high level operations like read, write, and abort. However, in a realistic setting, processors use relaxed memory models to optimize hardware performance. Moreover, the atomicity of operations depends on the underlying hardware. This paper presents the first approach to verify STMs under relaxed memory models with atomicity of 32 bit loads and stores, and read-modifywrite operations. We describe RML, a simple language for expressing concurrent programs. We develop a semantics of RML parametrized by a relaxed memory model. We then present our tool, FOIL, which takes as input the RML description of an STM algorithm restricted to two threads and two variables, and the description of a memory model, and automatically determines the locations of fences, which if inserted, ensure the correctness of the restricted STM algorithm under the given memory model. We use FOIL to verify DSTM, TL2, and McRT STM under the memory models of sequential consistency, total store order, partial store order, and relaxed memory order for two threads and two variables. Finally, we extend the verification results for DSTM and TL2 to an arbitrary number of threads and variables by manually proving that the structural properties of STMs are satisfied at the hardware level of atomicity under the considered relaxed memory models.

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“…At Sun and Stanford [30], researchers have used an axiomatic formulation of a memory model with randomized testing to find bugs in a transactional memory implementation. Finally, work at EPFL gives a correctness condition intended to rule out bugs like the privatization problem given above [12], and gives a set of conditions under which the verification problem reduces to two threads and two variables [10], [11].…”

Section: Related Workmentioning

confidence: 99%

“…Unfortunately, that result does not apply to our work: McRT uses update-in-place which is harder to validate than deferred-update, since updates by an aborting transaction can be visible to other transactions if the aborting transaction does not clean up properly. Coming work [11] describes an extension of this reduction to update-in-place and applies it to an abstract model of McRT.…”

Section: Introductionmentioning

confidence: 99%