SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory

Abstract

Several emerging technologies for byte-addressable non-volatile memory (NVM) have been considered to replace DRAM as the main memory in computer systems during the last years. The disadvantage of a lower write endurance, compared to DRAM, of NVM technologies like Phase-Change Memory (PCM) or Ferroelectric RAM (FeRAM) has been addressed in the literature. As a solution, in-memory wear-leveling techniques have been proposed, which aim to balance the wear-level over all memory cells to achieve an increased memory lifetime. Generally, to apply such advanced aging-aware wear-leveling techniques proposed in the literature, additional special hardware is introduced into the memory system to provide the necessary information about the cell age and thus enable aging-aware wearleveling decisions.This paper proposes software-only aging-aware wear-leveling based on common CPU features and does not rely on any additional hardware support from the memory subsystem. Specifically, we exploit the memory management unit (MMU), performance counters, and interrupts to approximate the memory write counts as an aging indicator. Although the software-only approach may lead to slightly worse wear-leveling, it is applicable on commonly available hardware. We achieve page-level coarsegrained wear-leveling by approximating the current cell age through statistical sampling and performing physical memory remapping through the MMU. This method results in nonuniform memory usage patterns within a memory page. Hence, we further propose a fine-grained wear-leveling in the stack region of C / C++ compiled software.By applying both wear-leveling techniques, we achieve up to 78.43% of the ideal memory lifetime, which is a lifetime improvement of more than a factor of 900 compared to the lifetime without any wear-leveling.

Relieving Compression-Induced Local Wear on Non-Volatile Memory Block via Sliding Writes

“…Huang et al [ 8 ] detected the number of writes to each physical block and wrote data to the physical block with the fewest writes. Hakert et al [ 9 ] used a red-black tree to estimate the age of blocks for wear leveling across pages. Xiao et al [ 10 ] used the wear counter to dynamically adjust the use of NVM slots to achieve wear leveling between blocks.…”

“…There are many studies on extending the lifetime of NVM, e.g., by keeping wear leveling among memory blocks [ 7 , 8 , 9 , 10 ], reducing the number of writes [ 11 , 12 ] or reducing the bit flips [ 13 , 14 , 15 , 16 ]. However, these methods often consume extra NVM space for the metadata, e.g., tag information in the most commonly used FNW method that is used to reduce bit flips [ 15 ].…”