SOI technology for the GHz era

Abstract

Silicon-on-insulator (SOI) CMOS offers a 20-35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-m generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-m generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

Physical limits of silicon transistors and circuits

“…This modification leads to substantial changes in the physics of the transistor (Taur and Ning 1998). SOI offers reduced power, faster operation and more efficient use of chip area as compared with devices in bulk silicon (Shahidi 2002). The replacement of part of the source and drain interfaces with bulk silicon by contact with the insulator reduces capacitances, and therefore reduces power dissipation and allows faster operation.…”

“…This 'double gate FET' also receives much attention (Doyle et al 2002, Shahidi 2002, Wong 2002, ITRS 2003, Lundstrom 2003 and is shown in figure 12. The confinement of the silicon between two parallel gates allows a larger source-drain current to be controlled.…”

Smart Cut TM SiCOI wafers for MBE GaN epitaxy

“…The most popular example is today SOI substrates (Silicon On Insulator) which are now used by most IC manufacturers who see in SOI substrates the opportunity to develop new high performance devices [1]. SOI substrates are also the first example of future thin film composite substrates that will bring even higher performance enhancements in the devices of the future.…”

Fabrication and thermal evaluation of silicon on diamond wafers

“…Future device layer thicknesses in SOI electronics are expected to be on the order of 100 nm. 4 Influence of the Si device layer thickness on thermal properties of SOD wafers will be assessed in detail in future experiments. Future studies will also include an analysis of the electronic properties of the Si device layer and especially the quality of the Si/diamond interface.…”

“…At identical feature size, ICs using SOI show a performance gain of 30% compared to ICs on bulk Si. 4 The SOI promises both advanced device performance and decreased power consumption. However, as the number of transistors on a chip grows, and the power losses continue to increase, 5 the thermal insulation of SiO 2 becomes a growing concern for the overall IC performance.…”