Solder Bump Electromigration and CPI Challenges in Low-k Devices

Abstract

Understanding and managing both chip-to-package interaction (CPI) and solder bump electromigration (EM) in new designs is becoming an increasing challenge for flip chip plastic ball grid array (FCPBGA) packaging. Requirements for state-of-the-art device technologies drive smaller features, higher power and RoHS compliance (Pb-free product). It will be shown that the optimal attributes for Pb-free solder bump EM performance often are diametrically opposed to the design parameters that improve CPI robustness in structures comprised of low-k dielectric materials.

Toward Successful Integration of Porous Low-k Materials: Strategies Addressing Plasma Damage

“…[3][4][5][6] The resulting structural changes in both density and networkconnectivity (as compared to SiO 2 ) negatively impacted the mechanical properties of the porous low-k materials, [7][8][9][10][11][12][13] leading in some cases to drastic failure during chip packaging. 14 This is currently solved by chip design, post-deposition treatments of existing low-k materials with a thermal ultraviolet (UV) source 15,16 or laser spike annealing (LSA) 17 and through the development of carbon-bridged materials with superior mechanical properties at a given k. [18][19][20][21][22][23] While the decrease in mechanical properties has been successfully addressed, integration problems related to the increased porosity with decreasing k are still pending. In case of the latter, the huge increase in accessible surface area leads to integration related damage, such as material modification occurring during exposure to plasma and wet chemical processes.…”

Ionic Conductivity of Lithium Based Electrolytes in the LiI-Li2O-MoO2-V2O5 (LMV) Quaternary Glass System

“…When the concentration of the lithium ion is low the conductivity will be low and as the level of the lithium ion increases the conductivity will increase as the Li + is the major source of ions for conduction. This increase in conductivity will occur up to the point at which the level of lithium ions becomes too high and begins to impede the movement of one-another by crowding (5). The graph of this should resemble a bell curve with the 60% to 70% dopant level near the top of the curve.…”

Process Challenges for Integration of Copper Interconnects with Low-k Dielectrics

“…Packaging process changes include optimizing the dicing process (two-step dicing or laser dicing, Fig. 12) [50][51][52] , the underfill (lower modulus) [53], the molding compound (lower coefficient of thermal expansion, CTE) [54], the solder composition, the solder reflow process, and the adhesion of the dielectrics and barrier layers in the low-k stack [46]. Figure 12.…”

“…For flip chip packages, the stress occurs underneath the solder bumps, (typically during chip joining) that can cause cracks in the low-k dielectrics. The problem becomes even more difficult with Pb-free solder, due to the high modulus and higher melting point of Pb-free solder compared to Pb-based solder [46]. Design and process changes must also be made to allow reliable packaging of these die.…”